Ampro Corporation Littleboard 550 manual Memory Control Options

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Chapter 4

BIOS Setup

Memory Control Options

Memory

Memory Test – [Fast], [Standard], or [Exhaustive]

If this field is set to [Fast], only basic memory tests are performed during POST to shorten POST time.

If this field is set to [Standard], more than basic tests are performed, but POST time is increased.

If this field is set to [Exhaustive], more rigorous tests are performed on memory, but this takes a significant amount of time for POST to complete.

Memory Hole – [Disabled], [1MB], or [2MB]

This field specifies the size of an optional memory hole, below 16MB. Access to the memory addresses inside the memory hole region are forwarded to the PC/104 bus, where memory mapped PC/104 devices have access.

Shadow D000-D3FF – [Disabled] or [Enabled]

These Shadow fields specify if BIOS option ROMs in the indicated segments should be shadowed to RAM. Shadowing option ROMs can potentially speed up the operation of the system. The indicated segments are only for option ROMs present on add-on PC/104 and PC/104-Plus cards.

Shadow D400-D7FF – [Disabled] or [Enabled]

Shadow D800-DBFF – [Disabled] or [Enabled]

Shadow DC00-DFFF – [Disabled] or [Enabled]

DRAM

NOTE

The DRAM clock frequency can never be set higher than

 

the CPU’s Front Side Bus (FSB) clock frequency,

 

regardless of the SPD or PC100 setting.

 

 

DRAM Clock Frequency – [SPD] or [PC100] This field specifies the DRAM clock frequency.

If this field is set to SPD (Serial Presence Detect), then the DRAM clock is set using the information read from the SPD(s) on the DRAM module(s).

If this field is set to PC100, the clock will override the DRAM SPD information and force the DRAM clock to 100MHz.

DRAM CAS Latency – [SPD], [CAS 3], or [CAS 2]

This field specifies the DRAM CAS (Column Address Strobe) Latency

If this field is set to SPD, then the DRAM CAS latency is set using the information read from the SPD(s) on the DRAM module(s).

If this field is set to CAS 2 or CAS 3, the setting will override the DRAM SPD information and force the DRAM CAS latency to the specified value.

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Reference Manual

LittleBoard 550

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Contents LittleBoard Single Board Computer Reference Manual Audience Assumptions Contents Appendix a List of Tables Table A-1 Purpose of this Manual SpecificationsReference Material LittleBoard 550 Support Products Related Ampro ProductsOther LittleBoard Products Other Ampro Products Chapter Product Overview EBX ArchitectureProduct Description Stacking PC/104 Modules with the LittleBoardBoard Features Chapter Chapter Block Diagram ATAMajor Integrated Circuits ICs Chip Type Mfg Model Description FunctionVIA CPUConnector Definitions Jack # Signal DescriptionAdditional Components DIMM1Northb Jumper # Installed Removed/Installed DefaultIndicator Definition Jumper DefinitionsThb Physical Specifications SpecificationsDimension Mechanical Specifications LittleBoard 550 Dimensions Top view, #1115 705 415 730 200 050 350 800 600 385 345 Environmental Specifications Power SpecificationsThermal/Cooling Requirements Reference Manual LittleBoard Overview USBCPU U1 MemorySdram Memory DIMM1 Flash Memory U17Interrupt Channel Assignments Memory MapAddress Map Base Address FunctionAddress hex Subsystem VGAPin # Signal Input Description Output PC/104-Plus Interface J21IDSEL0 REQ0GNT1 CLK2REQ2 CLK0Intd IntaIDSEL1 REQ1GNT2 CLK3IDSEL2 IDSEL3GNT0 CLK1Pin # Signal Description J1 Row a PC/104 Interface J1A,B,C,DPin # Signal Descriptions J1 Row B DACK3 DRQ3DACK1 DRQ1Pin # Signal Descriptions J1 Row C Pin # Signal Descriptions J1 Row DIRQ15 IRQ14DACK0 DRQ0Pin # Signal Description IDE Interface J12, J17Pdreq PdiowPdior PdiordySDD8 SDD6SDD9 SDD5SDA1 SDA0SDA2 SDCS1#PDCE1 CompactFlash Adapter J23VCC PDCE2 PdrstFloppy Drive Interface J14 Pin # Signal In/Out Description Parallel Port Interface J15Serial Interfaces J11, J13 RS485 Serial Port ImplementationDCD1 DSR1RXD1 RTS1CTS2 DTR2DCD3 DSR3DCD4 DSR4RXD4 RTS4Utility Interfaces Utility 1 Interface J16Mouse Interface Utility 2 Interface J24System Management Bus SMBus Component Address Binary USB Signals USB0 and USB1Sdram Eprom Susc PwrbtBatlow MdataUSB Signals USB2 and USB3 Utility 3 Interface J18Ethernet Interfaces J7, J32 TX+Audio Interface J28 Videol VideogndVideor CDLVideo Interfaces J3, J4, J5, J31 CRT InterfaceLCD Interface Enavdd Pin # Signal Description Line Channel Lvds InterfaceTemperature Monitoring Oops! Jumper Bios RecoveryMiscellaneous Real Time Clock RTCWatchdog Timer Hot Cable JumperPower Interface J10 Power MonitorCPU Fan TAGReference Manual LittleBoard Accessing Bios Setup VGA Display IntroductionAccessing Bios Setup Serial Console Bios Setup Menu Item/TopicBios Menus Bios Setup Opening ScreenBios Configuration Screen Drive Configurations and Boot OptionsDate & Time Drive Assignment# of Floppy Drives Bios Settings Boot Order Drive and Boot OptionsUser Interface Options Keyboard and Mouse ConfigurationUser Interface Memory Control Options MemoryPower Management Power Management and Advanced User OptionsAdvanced features On-Board Serial Ports On-Board LPT Port On-Board Controllers Video, Flat Panel, and Audio OptionsOn-Board Video PCI, Plug n Play, and Interrupt Assignments Chapter Bios Setup Chapter Bios Setup Chapter Bios Setup Splash Screen Image Requirements Splash Screen CustomizationConverting the Splash Screen File \splashconvert convert.idf Appendix a Technical Support Method Contact InformationAppendix a Technical Support Connector Designation Pin # Mfg Part Number Appendix B Appendix C LAN Boot Option PXE Boot Agent Bios Setup Accessing PXE Boot Agent Bios SetupPXE Configuration PXE Boot Agent Setup ScreenTCP/IP Configuration NetWare Configuration RPL ConfigurationCD-ROM CRTDocumentation and Support Software Doc & SW CD-ROM PostSupported features WDTReference Manual LittleBoard