Samsung M8 manual Host Interface Control Block, Buffer Control Block

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5.2.2.1The Host Interface Control Block

The SATA Disk Controller provides direct interface to an SATA bus. It is compatible with ATA 7 Specs. It provides a means for the host to access the Task File registers used to control the transfer of data between host memory and the disk drive.

The SATA Host Interface Control block can be programmed to execute various host read/write commands either completely automatically without any DSP intervention, semi-automatically with minimal DSP intervention, or manually with the aid of the DSP.

The Disk Controller has significant advances in ATA automation. The highlights of ATA automation includes:

Automatic data transfer management for multi-sector Read/Write commands without DSP intervention.

Automatic execution of read commands (Auto-Read command execution) for cached data in the buffer by matching the first sector.

Automatic Task File registers updates during automatic multi-sector transfers.

Automatic NCQ queue tag validation

Spinpoint M8 supports PIO, DMA, and FPDMA data transfers. The supported DMA type transfers include multi-

word (MWDMA) and synchronous Ultra DMA (UDMA) transfers. The bus emulates automatically switched between 16- and 8-bit mode while performing Read Long and Write Long commands at the time of ECC byte transfers.

Additional functionality is provided in the Host Interface Block by the following features:

Programmable transfer length for automatic ECC byte transfer on the AT bus.

Support of both LBA and CHS Task File registers formats.

Automatic detection of both the Software Reset and COMRESET.

Support for PIO modes 0 through 4.

Support for multiword DMA modes 0 through 2.

Support for multiword DMA modes 0 through 2. Support for synchronous DMA (UDMA) transfer mode 0 through 7. (Mode 7 is referring to 150 MB/S)

Support for First Party DMA (FDMA) for NCQ commands.

5.2.2.2The Buffer Control Block

The Buffer Control block manages the flow of data into and out of the buffer. Significant automation allows buffer activity to take place automatically during read/write operations between the host and the disk. This automation works together with automation within the Host Interface Control and Disk Control blocks to provide more bandwidth for the local microprocessor to perform non-data flow functions.

The buffer control circuitry keeps track of buffer full and empty conditions and automatically works with the Disk Control block to stop transfers to or from the disk when necessary. In addition, transfers to or from the host are automatically stopped or started based on buffer full or empty status.

A prioritized five ports architecture is implemented. All ports, except the refresh port, utilize 22-bit buffer address pointers.

The data path to the buffer RAM can be configured as 16-bit path in ATA mode.

Spinpoint M8 Product Manual REV 2.3

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Contents M8 Product Manual Page Table of Contents Servo System Read and Write Operations Read Fpdma Queued 60h Read Log Extended 2Fh Read Long 22h Table of Tables User Definition ScopeManual Organization Sata ReferenceDescription IntroductionKey Features Standards and Regulations Hardware RequirementsSpecifications SpecificationsSpecification Summary Spindle speed RPM RPM ClassPhysical Specifications Physical SpecificationsLogical Configurations Physical dimensionsPerformance Specifications Power Requirements Power consumptionPower consumption RatedEnvironmental Specifications Environmental Specifications15.0 Reliability Specifications Installation Space RequirementsUnpacking Instructions MountingMounting Dimensions OrientationClearance Mounting-Screw ClearanceVentilation Cable ConnectorsSata Connectivity Serial ATA Power ManagementHDD Power, Sata Interface, and Factory Jumper Connector Pin Locations on the Drive Pcba Drive Installation DC Power Connector and SATA-Bus Interface Cable ConnectionsDC Spindle Motor Assembly Head / Disk Assembly HDABase Casting Assembly Disk Drive OperationCoverAssembly Voice Coil Motor and Actuator Latch Assemblies Disk Stack AssemblyHead Stack Assembly Air Filtration SystemDrive Electronics Digital Signal Process and Interface ControllerDisk Controller DDR Host Interface Control Block Buffer Control BlockDisk Ldpc Control Block Disk Control BlockFrequency Synthesizer Time Base Generator Power ManagementRead/Write IC Automatic Gain ControlAnalog Anti-Aliasing Low Pass Filter Analog to Digital Converter ADC and FIRRead and Write Operations Servo SystemRead Channel Write Channel Firmware FeaturesRead Caching Write Caching Multi-burst ECC Correction Defect ManagementAutomatic Defect Allocation SmartSata II Interface Sata TerminologySpinpoint M8 Product Manual REV Physical Interface Signal Summary Signal DescriptionsControl Block Register Descriptions When read When written2 I/O Register Address RegistersError Register Ex F1h Command Block Register DescriptionsFeatures Register and Feature Extended Register Ex F1h Device Control Register ex F6hCommand Register Ex F7h Device Register Ex F6hStatus Register Ex F7h Staggered Spin-up Disable Control Sata II Feature SETDevice Activity Signal Auto-Activate in DMA Setup FISPhy. Event Counters Software Settings Preservation Sata Power ManagementCommand Table ATA Command DescriptionsCommand Code Parameters Command Descriptions Check Power Mode E5hCommand Device Configuration Overlay B1hDevice Configuration Overlay Feature Register Values Download Micro Code 92hDevice Configuration Identify data structure Word Content Flush Cache E7h, EAh extended Execute Device Diagnostics 90hDiagnostic Codes Format Track 50hContent Description Identify Device information=the fields reported in word 88 are valid EXT =Media Card Pass Through command feature set supported Word Content Description WWNIdle E3h Automatic Standby Timer PeriodsIdle Immediate E1h Read Buffer E4h Initialize Device Parameters 91hNOP 00h Read DMA C8h, 25h extendedRead Log Extended 2Fh Read Multiple Command C4h, 29h extendedRead Long 22h Read Sectors 20h, 24h extended Read Native Max Address F8h, 27h extendedRead Verify Sectors 40h, 41h extended Security Erase Prepare F3h Security Disable Password F6hRecalibrate 10h Security Erase Unit F4hSecurity Set Password data content Security Set Password F1hSecurity Erase Unit Password Word Content Security Freeze Lock F5hSecurity Unlock F2h Set Features EFhIdentifier Level Command result Seek 7xh11 Set Features Register Definitions 12 Transfer Mode ValuesSet Max Address F9h, 37h extended Set Multiple Mode C6h13 Set Max Feature Register Values Sleep E6hSmart enable/disable attribute auto-save D2h 14 Smart Feature Registers ValuesSmart disable operations D9h Smart B0hSmart enable operations D8h Smart execute off-line immediate D4hSmart read data D0h 15 Device Smart Data StructureData Structure Revision Number Bit Name Description 16 Smart Attribute Status Flags17 Smart Attribute Data List 18 Off-line Data Collection Status ValuesSelf-test execution status byte 19 Self-test Execution Status ValuesSmart return status DAh Smart read log sector D5hSmart write log sector D6h Write DMA CAh, 35h extended Standby Immediate E0hWrite Buffer E8h Write Fpdma Queued 61hWrite Long 32h Write Multiple Command C5h, 39h extendedWrite Sectors 30h, 34h extended Spinpoint M8 Product Manual REV Maintenance Precautions MaintenanceGeneral Information HDD handling guide -Please handle HDD by side surfaces Service and Repair HDD handling guide Prevent Shocks
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