Advantech PCM-3780 manual Programmable Counter, Digital Input/Output

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Appendix A Specifications

A.1 Programmable Counter

	Channels	2

	Resolution	16-bit

	Compatibility	TTL level

	Max. Input	20 MHz
	Frequency

	Clock Input	Low	0.8	V max.

		High	2.0	V min.
		High	2.0	V min.

	Gate Input	Low	0.8	V max.

		High	2.0	V min.
		High	2.0	V min.

	Counter Output	Low	0.4	V max.@ +8.0mA (sink)

		High	2.4	V min.@ -0.4mA(source)
		High	2.4	V min.@ -0.4mA(source)

A.2 Digital Input/Output

	Channels	24 (8255Mode 0)

	Input Voltage	Low	0.4V max.

		High	2.4 V min.
		High	2.4 V min.

	Input Load	Low	0.4 V max.@ -0.2mA

		High	2.7 V min.@20µA
		High	2.7 V min.@20µA

	Output Voltage	Low	0.5 V max.@+24 mA

		High	2.4 V min.@-15 mA
		High	2.4 V min.@-15 mA

PCM-3780 User Manual

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Contents Ch Counter/Timer with Ch TTL DIO Module PCM-3780Copyright Acknowledgements Two Years Product Warranty CE Notification FCC Class a Technical Support and Assistance Packing List Page Contents Appendix Specifications Introduction Features PCM-3780 Counter Mode Counter ModesPCM-3780 Counter Mode Installation Guide ApplicationsInstallation Flow Chart Device Drivers Software OverviewDevice Drivers on the companion CD-ROM Register-level ProgrammingDevice Drivers Programming Roadmap Programming ToolsTroubleshooting Device Drivers Error Programming with Device Drivers Function LibraryWiring Cables AccessoriesWiring Boards Hardware Installation Unpacking Driver Installation Companion CD-ROMDifferent Options for Driver Setup Hardware Installation Installing the ModulePage Pin Assignments & Jumper Settings Signal Connections OverviewSwitch and Jumper Settings Interrupt Level IRQ Setting JP1Base Address Setting SW1 Base Address SettingCN3 I/O Port Connector Connectors Pin AssignmentCN4 Counter Interface Connector Connector Signal Description Reference Direction DescriptionUsing Direct I/O Using Advantech 32-bit DLL DriverPeriod Measurement Frequency Measurement Frequency MeasurementSpecifications Programmable Counter Digital Input/OutputGeneral Page Block Diagram Appendix B Block Diagram Register Structure & Format Appendix C Register Structure & Format I/O Port Address MapRegister Format Table C.1 Register Offset Address TableCE CE CM1 to CM0 Output Control Counter 0/1 Mode RegisterCM2 Output Enable Control CM6 to CM3 Count Control CM6CM14 Gating Polarity Selection CM7 Count Source EdgeCM13 to CM12 Gate Source Selection CM15 Gate Active Edge or LevelCounter 0/1 Load Register Counter 0/1 Hold RegisterC2 to C0 Command Code Counter 0/1 Command RegisterCounter Command Enable Register CE1 to CE0 Counter Command Enable BitInterrupt Control Register Interrupt Status RegisterPort A/B/C Interrupt Status Register Interrupt Clear RegisterDirection Control Register O Direction Control BitFout Register DV3 to DV0 Fout Divider Divide by 1 to 16 0000 = Divide byFOE Fout Output Enable FS2 to FS0 Fout SourceWaveform of Each Mode Appendix D Waveform of Each Mode Counter Mode DescriptionsTable D.1 PCM-3780 Counter Mode Table D.2 PCM-3780 Counter Mode Mode a Waveforms Software-Triggered Strobe with No Hardware GatingMode B Waveforms Software-Triggered Strobe with Level GatingMode C Waveforms Hardware-Triggered StrobeMode D Waveforms Rate Generator with No Hardware GatingMode E Waveforms Rate Generator with Level GatingMode F Waveforms Non-Retriggerable One-ShotMode G Waveforms Software-Triggered Delayed Pulse One-ShotMode H Waveforms Mode I Waveforms Hardware-Triggered Delayed Pulse StrobeMode J Waveforms Variable Duty Cycle Rate Generator with No Hardware GatingMode K Waveforms Variable Duty Cycle Rate Generator with Level GatingMode L Waveforms Hardware-Triggered Delayed Pulse One-ShotMode O Waveforms Hardware-Triggered Strobe with Edge DisarmMode R Waveforms Non-Retriggerbale One-Shot with Edge DisarmMode U Waveforms Hardware-Triggered Delayed Pulse Strobe with Edge DisarmMode X Waveforms Hardware-Triggered Delayed Pulse One-Shot with Edge Disarm