Advantech PCM-3780 manual CM7 Count Source Edge, CM13 to CM12 Gate Source Selection

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CM3:

0 = Count Down

1 = Count Up

4.CM7: Count Source Edge

0= Count on Rising Edge

1= Count on Falling Edge

5.CM11 to CM8: Count Source Selection 0000 = Internal Clock (20MHz)

0001 = OUT N-1

0010 = CLK N

0011 = CLK N-1

0100 = FOUT0

0101 = FOUT1

0111 = GATE N-1

6.CM13 to CM12: Gate Source Selection

00= No Gating

01= OUT N-1

10= GATE N

11= GATE N-1

7.CM14: Gating Polarity Selection

0 = High Level for Level Active, Rising Edge for Edge Active 1 = Low Level for Level Active, Falling Edge for Edge Active

8.CM15: Gate Active Edge or Level

0= Level Active

1= Edge Active

PCM-3780 User Manual

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Contents Ch Counter/Timer with Ch TTL DIO Module PCM-3780Copyright Acknowledgements Two Years Product Warranty CE Notification FCC Class a Technical Support and Assistance Packing List Page Contents Appendix Specifications Introduction Features PCM-3780 Counter Mode Counter ModesPCM-3780 Counter Mode Installation Guide ApplicationsInstallation Flow Chart Software Overview Device Drivers on the companion CD-ROMDevice Drivers Register-level ProgrammingDevice Drivers Programming Roadmap Programming ToolsTroubleshooting Device Drivers Error Programming with Device Drivers Function LibraryWiring Boards AccessoriesWiring Cables Hardware Installation Unpacking Driver Installation Companion CD-ROMDifferent Options for Driver Setup Hardware Installation Installing the ModulePage Pin Assignments & Jumper Settings Signal Connections OverviewSwitch and Jumper Settings Interrupt Level IRQ Setting JP1Base Address Setting SW1 Base Address SettingCN4 Counter Interface Connector Connectors Pin AssignmentCN3 I/O Port Connector Connector Signal Description Reference Direction DescriptionPeriod Measurement Using Advantech 32-bit DLL DriverUsing Direct I/O Frequency Measurement Frequency MeasurementSpecifications Programmable Counter Digital Input/OutputGeneral Page Block Diagram Appendix B Block Diagram Register Structure & Format Appendix C Register Structure & Format I/O Port Address MapRegister Format Table C.1 Register Offset Address TableCE CE Counter 0/1 Mode Register CM2 Output Enable ControlCM1 to CM0 Output Control CM6 to CM3 Count Control CM6CM7 Count Source Edge CM13 to CM12 Gate Source SelectionCM14 Gating Polarity Selection CM15 Gate Active Edge or LevelCounter 0/1 Load Register Counter 0/1 Hold RegisterCounter 0/1 Command Register Counter Command Enable RegisterC2 to C0 Command Code CE1 to CE0 Counter Command Enable BitInterrupt Control Register Interrupt Status RegisterInterrupt Clear Register Direction Control RegisterPort A/B/C Interrupt Status Register O Direction Control BitFout Register DV3 to DV0 Fout Divider Divide by 1 to 16 0000 = Divide byFOE Fout Output Enable FS2 to FS0 Fout SourceWaveform of Each Mode Appendix D Waveform of Each Mode Counter Mode DescriptionsTable D.1 PCM-3780 Counter Mode Table D.2 PCM-3780 Counter Mode Mode a Waveforms Software-Triggered Strobe with No Hardware GatingMode B Waveforms Software-Triggered Strobe with Level GatingMode C Waveforms Hardware-Triggered StrobeMode D Waveforms Rate Generator with No Hardware GatingMode E Waveforms Rate Generator with Level GatingMode F Waveforms Non-Retriggerable One-ShotMode G Waveforms Software-Triggered Delayed Pulse One-ShotMode H Waveforms Mode I Waveforms Hardware-Triggered Delayed Pulse StrobeMode J Waveforms Variable Duty Cycle Rate Generator with No Hardware GatingMode K Waveforms Variable Duty Cycle Rate Generator with Level GatingMode L Waveforms Hardware-Triggered Delayed Pulse One-ShotMode O Waveforms Hardware-Triggered Strobe with Edge DisarmMode R Waveforms Non-Retriggerbale One-Shot with Edge DisarmMode U Waveforms Hardware-Triggered Delayed Pulse Strobe with Edge DisarmMode X Waveforms Hardware-Triggered Delayed Pulse One-Shot with Edge Disarm