Advantech PCM-3780 Mode U Waveforms, Hardware-Triggered Delayed Pulse Strobe with Edge Disarm

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D.16 Mode U Waveforms

Hardware-Triggered Delayed Pulse Strobe with Edge Disarm

Mode U is identical to Mode I except that the counter will be disarmed while the gate and inactive-going gate edge is applied to the counter. The counter will hold the count value until it is issued a LOAD command or REST command.

SOURCE

WR

GATE

COUNT

VALUE

TC OUTPUT

TC TOGGLED OUTPUT

SOURCE

WR

GATE

COUNT

VALUE

TC OUTPUT

TC TOGGLED OUTPUT

SOURCE

WR

GATE

COUNT

VALUE

TC OUTPUT

TC TOGGLED OUTPUT

ARM

COMMAND

X

L

L-1

L-2

2

1

0

H

H-1

H-2

2

1

0

L

ARM

COMMAND

X

L

L-1

L-2

2

1

0

H

H-1

H-2

N+2

N+1

N

ARM

COMMAND

X

L

L-1

L-2

N+2

N+1

N

Mode U Waveforms

61

AppendixD

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Contents PCM-3780 Ch Counter/Timer with Ch TTL DIO ModuleCopyright Acknowledgements Two Years Product Warranty CE Notification FCC Class a Technical Support and Assistance Packing List Page Contents Appendix Specifications Introduction Features Counter Modes PCM-3780 Counter ModePCM-3780 Counter Mode Applications Installation GuideInstallation Flow Chart Device Drivers on the companion CD-ROM Software OverviewDevice Drivers Register-level ProgrammingProgramming Tools Device Drivers Programming RoadmapProgramming with Device Drivers Function Library Troubleshooting Device Drivers ErrorAccessories Wiring CablesWiring Boards Hardware Installation Unpacking Companion CD-ROM Driver InstallationDifferent Options for Driver Setup Installing the Module Hardware InstallationPage Pin Assignments & Jumper Settings Overview Signal ConnectionsInterrupt Level IRQ Setting JP1 Switch and Jumper SettingsBase Address Setting Base Address Setting SW1Connectors Pin Assignment CN3 I/O Port ConnectorCN4 Counter Interface Connector Reference Direction Description Connector Signal DescriptionUsing Advantech 32-bit DLL Driver Using Direct I/OPeriod Measurement Frequency Measurement Frequency MeasurementSpecifications Digital Input/Output Programmable CounterGeneral Page Block Diagram Appendix B Block Diagram Register Structure & Format I/O Port Address Map Appendix C Register Structure & FormatTable C.1 Register Offset Address Table Register FormatCE CE CM2 Output Enable Control Counter 0/1 Mode RegisterCM1 to CM0 Output Control CM6 to CM3 Count Control CM6CM13 to CM12 Gate Source Selection CM7 Count Source EdgeCM14 Gating Polarity Selection CM15 Gate Active Edge or LevelCounter 0/1 Hold Register Counter 0/1 Load RegisterCounter Command Enable Register Counter 0/1 Command RegisterC2 to C0 Command Code CE1 to CE0 Counter Command Enable BitInterrupt Status Register Interrupt Control RegisterDirection Control Register Interrupt Clear RegisterPort A/B/C Interrupt Status Register O Direction Control BitDV3 to DV0 Fout Divider Divide by 1 to 16 0000 = Divide by Fout RegisterFS2 to FS0 Fout Source FOE Fout Output EnableWaveform of Each Mode Counter Mode Descriptions Appendix D Waveform of Each ModeTable D.1 PCM-3780 Counter Mode Table D.2 PCM-3780 Counter Mode Software-Triggered Strobe with No Hardware Gating Mode a WaveformsSoftware-Triggered Strobe with Level Gating Mode B WaveformsHardware-Triggered Strobe Mode C WaveformsRate Generator with No Hardware Gating Mode D WaveformsRate Generator with Level Gating Mode E WaveformsNon-Retriggerable One-Shot Mode F WaveformsSoftware-Triggered Delayed Pulse One-Shot Mode G WaveformsMode H Waveforms Hardware-Triggered Delayed Pulse Strobe Mode I WaveformsVariable Duty Cycle Rate Generator with No Hardware Gating Mode J WaveformsVariable Duty Cycle Rate Generator with Level Gating Mode K WaveformsHardware-Triggered Delayed Pulse One-Shot Mode L WaveformsHardware-Triggered Strobe with Edge Disarm Mode O WaveformsNon-Retriggerbale One-Shot with Edge Disarm Mode R WaveformsHardware-Triggered Delayed Pulse Strobe with Edge Disarm Mode U WaveformsHardware-Triggered Delayed Pulse One-Shot with Edge Disarm Mode X Waveforms