Transcend Information CF 266X dimensions „ Additional Requirements for CF Advanced Timing Modes

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TS2G~8GCF266

266X CompactFlash Card

 

 

 

Notes: 1) Control Signals: each card shall present a load to the socket no larger than 50 pF 10 at a DC current of 700 μA low state and 150 μA high state, including pull-resistor. The socket shall be able to drive at least the following load 10 while meeting all AC timing requirements: (the number of sockets wired in parallel) multiplied by (50 pF with DC current 700 μA low state and 150 μA high state per socket).

2)Resistor is optional.

3)Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 μA low

state and 100 μA high state, including pull-up resistor. The card shall be able to drive at least the following load 10 while meeting all AC timing requirements: 50 pF at a DC current of 400 μA low state and 100 μA high state.

4)Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 μA low state and 100 μA high state, including pull-up resistor. The card shall be able to drive at least the following load 10 while meeting all AC timing requirements: 50 pF at a DC current of 400 μA low state and 100 μA high state.

5)Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 μA low state and 100 μA high state, including pull-up resistor. The card shall be able to drive at least the following load 10 while meeting all AC timing requirements: 50 pF at a DC current of 400 μA low state and 1100 μA high state.

6)BVD2 was not defined in the JEIDA 3.0 release. Systems fully supporting JEIDA release 3 SRAM cards shall pull-up pin 45 (BVD2) to avoid sensing their batteries as “Low.”

7)Address Signals: each card shall present a load of no more than 100pF 10 at a DC current of 450μA low state and 150μA high state. The host shall be able to drive at least the following load 10 while meeting all AC timing requirements: (the number of sockets wired in parallel) multiplied by (100pF with DC current 450μA low state and 150μA high state per socket).

8)Data Signals: the host and each card shall present a load no larger than 50pF 10 at a DC current of 450μA and 150μA high state. The host and each card shall be able to drive at least the following load 10 while meeting all AC

timing requirements: 100pF with DC current 1.6mA low state and 300μA high state. This permits the host to wire two sockets in parallel without derating the card access speeds.

9)Reset Signal: This signal is pulled up to prevent the input from floating when a CFA to PCMCIA adapter is used in a PCMCIA revision 1 host. However, to minimize DC current drain through the pull-up resistor in normal operation the pull-up should be turned off once the Reset signal has been actively driven low by the host. Consequently, the input is specified as an I2Z because the resistor is not necessarily detectable in the input current leakage test.

10)Host and card restrictions for CF Advanced Timing Modes and Ultra DMA modes: Additional Requirements for CF Advanced Timing Modes and Ultra DMA Electrical Requirements for additional required limitations on the implementation of CF Advanced Timing modes and Ultra DMA modes respectively.

„Additional Requirements for CF Advanced Timing Modes

The CF Advanced Timing modes include PCMCIA I/O and Memory modes that are 100ns or faster and True IDE PIO Modes 5,6 and Multiword DMA Modes 3,4.

When operating in CF Advanced timing modes, the host shall conform to the following requirements:

1)Only one CF device shall be attached to the CF Bus.

2)The host shall not present a load of more than 40pF to the device for all signals, including any cabling.

3)The maximum cable length is 0.15 m (6 in). The cable length is measured from the card connector to the host controller. 0.46 m (18 in) cables are not supported.

4)The -WAIT and IORDY signals shall be ignored by the host.

Devices supporting CF Advanced timing modes shall also support slower timing modes, to ensure operability with systems that do not support CF Advanced timing modes

Transcend Information Inc.

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Contents 266X CompactFlash Card Placement FeaturesDimensions DescriptionTranscend Block Diagram Pin Assignments and Pin Type TS2G~8GCF266 Signal Description TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 Electrical Specification „ Output Drive Type „ Output Drive Characteristics „ Signal Interface „ Additional Requirements for CF Advanced Timing Modes ¾ Series termination required for Ultra DMA operation 266X CompactFlash Card„ Ultra DMA Electrical Requirements Table Typical Series Termination for Ultra DMA¾ Ultra DMA Mode Cabling Requirement „ Attribute Memory Read Timing Specification TS2G~8GCF266 „ Common Memory Read Timing Specification „ Common Memory Write Timing Specification „ I/O Input Read Timing Specification TS2G~8GCF266 „ I/O Output Write Timing Specification TS2G~8GCF266 „ True IDE PIO Mode Read/Write Timing Specification TS2G~8GCF266 „ True IDE Ultra DMA Mode Read/Write Timing Specification Table Ultra DMA Data Burst Timing266X CompactFlash Card TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 „ Multiple Function CF+ Cards Card Configuration„ Single Function CF+ Cards TS2G~8GCF266 „ Attribute Memory Function Attribute Memory FunctionTS2G~8GCF266 TS2G~8GCF266 „ Pin Replacement Register Base + 04h in Attribute Memory „ Socket and Copy Register Base + 06h in Attribute Memory Table Pcmcia Mode I/O Function Transfer FunctionCommon Memory Transfer Function Table Common Memory FunctionTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol „ I/O Primary and Secondary Address Configurations Table Primary and Secondary I/O Decoding„ Contiguous I/O Mapped Addressing Table Contiguous I/O Decoding„ True IDE Mode Addressing „ Memory Mapped Addressing„ CF-ATA Registers ¾ Data Register Address 1F0h170hOffset 0,8,9¾ Cylinder High LBA 23-16 Register Address 1F5h175h Offset ¾ Sector Count Register Address 1F2h172h Offset¾ Sector Number LBA 7-0 Register Address 1F3h173h Offset ¾ Drive/Head LBA 27-24 Register Address 1F6h176h OffsetTS2G~8GCF266 ¾ Device Control Register Address 3F6h376h Offset Eh ¾ Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set „ Check Power Mode 98h or E5h „ Execute Drive Diagnostic 90h „ Erase Sectors C0h„ Flush Cache E7h „ Format Track 50h„ Identify Device Ech 266X CompactFlash Card ¾ Word 0 General Configuration ¾ Word 6 Default Number of Sectors per Track ¾ Word 1 Default Number of Cylinders¾ Word 3 Default Number of Heads ¾ Word 49 Capabilities Bit 13 Standby Timer¾ Translation Parameters Valid ¾ Multiple Sector Setting¾ Total Sectors Addressable in LBA Mode ¾ Current Number of Cylinders, Heads, Sectors/Track¾ Recommended Multiword DMA transfer cycle time ¾ Words 82-84 Features/command sets supported¾ Word 65 Minimum Multiword DMA transfer cycle time ¾ Word 68 Minimum PIO transfer cycle time with Iordy¾ Words 85-87 Features/command sets enabled ¾ Word 88 Ultra DMA Modes Supported and Selected ¾ Word 89 Time required for Security erase unit completion¾ Word 128 Security Status Bit 8 Security Level ¾ Word 91 Advanced power management level value¾ Word 160 Power Requirement Description Additional Requirements for CF Advanced Timing ModesTS2G~8GCF266 „ Idle 97h or E3h „ NOP 00h „ Idle Immediate 95h or E1h„ Initialize Drive Parameters 91h „ Read Buffer E4h „ Read DMA C8h „ Read Long Sector 22h or 23hTS2G~8GCF266 „ Recalibrate 1Xh „ Request Sense 03h „ Seek 7Xh „ Set Features EFh Feature Supported 266X CompactFlash Card „ Standby Immediate 94h or E0h „ Translate Sector 87h Translate Sector Information„ Wear Level F5h „ Write Buffer E8h „ Write DMA CAh TS2G~8GCF266 TS2G~8GCF266 „ Error Posting TS2G~8GCF266
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