Transcend Information CF 266X CF-ATA Registers, ¾ Data Register Address 1F0h170hOffset 0,8,9

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TS2G~8GCF266		266X CompactFlash Card

CF-ATA Registers

The following section describes the hardware registers used by the host software to issue commands to the CompactFlash device. These registers are often collectively referred to as the “task file.”

¾Data Register (Address - 1F0h[170h];Offset 0,8,9)

The Data Register is a 16 bit register, and it is used to transfer data blocks between the CompactFlash Storage Card data buffer and the Host. This register overlaps the Error Register.

Error Register (Address - 1F1h[171h]; Offset 1, 0Dh Read Only)

This register contains additional information about the source of an error when an error is indicated in bit 0 of the Status register.

This register is also accessed in PC Card Modes on data bits D15-D8 during a read operation to offset 0 with -CE2 low and -CE1 high.

Bit 7 (BBK/ICRC): this bit is set when a Bad Block is detected. This bit is also set when an interface CRC error is detected in True IDE Ultra DMA modes of operation.

Bit 6 (UNC): this bit is set when an Uncorrectable Error is encountered.

Bit 5: this bit is 0.

Bit 4 (IDNF): the requested sector ID is in error or cannot be found.

Bit 3: this bit is 0.

Bit 2 (Abort) This bit is set if the command has been aborted because of a CompactFlash Storage Card status condition: (Not Ready, Write Fault, etc.) or when an invalid command has been issued.

Bit 1 This bit is 0.

Bit 0 (AMNF) This bit is set in case of a general error.

Transcend Information Inc.

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Contents Description Placement FeaturesDimensions 266X CompactFlash CardTranscend Block Diagram Pin Assignments and Pin Type TS2G~8GCF266 Signal Description TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 Electrical Specification „ Output Drive Type „ Output Drive Characteristics „ Signal Interface „ Additional Requirements for CF Advanced Timing Modes Table Typical Series Termination for Ultra DMA 266X CompactFlash Card„ Ultra DMA Electrical Requirements ¾ Series termination required for Ultra DMA operation¾ Ultra DMA Mode Cabling Requirement „ Attribute Memory Read Timing Specification TS2G~8GCF266 „ Common Memory Read Timing Specification „ Common Memory Write Timing Specification „ I/O Input Read Timing Specification TS2G~8GCF266 „ I/O Output Write Timing Specification TS2G~8GCF266 „ True IDE PIO Mode Read/Write Timing Specification TS2G~8GCF266 Table Ultra DMA Data Burst Timing „ True IDE Ultra DMA Mode Read/Write Timing Specification266X CompactFlash Card TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 „ Multiple Function CF+ Cards Card Configuration„ Single Function CF+ Cards TS2G~8GCF266 Attribute Memory Function „ Attribute Memory FunctionTS2G~8GCF266 TS2G~8GCF266 „ Pin Replacement Register Base + 04h in Attribute Memory „ Socket and Copy Register Base + 06h in Attribute Memory Transfer Function Table Pcmcia Mode I/O FunctionTable Common Memory Function Common Memory Transfer FunctionTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Table Primary and Secondary I/O Decoding „ I/O Primary and Secondary Address ConfigurationsTable Contiguous I/O Decoding „ Contiguous I/O Mapped Addressing„ Memory Mapped Addressing „ True IDE Mode Addressing¾ Data Register Address 1F0h170hOffset 0,8,9 „ CF-ATA Registers¾ Drive/Head LBA 27-24 Register Address 1F6h176h Offset ¾ Sector Count Register Address 1F2h172h Offset¾ Sector Number LBA 7-0 Register Address 1F3h173h Offset ¾ Cylinder High LBA 23-16 Register Address 1F5h175h OffsetTS2G~8GCF266 ¾ Device Control Register Address 3F6h376h Offset Eh ¾ Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set „ Check Power Mode 98h or E5h „ Erase Sectors C0h „ Execute Drive Diagnostic 90h„ Format Track 50h „ Flush Cache E7h„ Identify Device Ech 266X CompactFlash Card ¾ Word 0 General Configuration ¾ Word 49 Capabilities Bit 13 Standby Timer ¾ Word 1 Default Number of Cylinders¾ Word 3 Default Number of Heads ¾ Word 6 Default Number of Sectors per Track¾ Current Number of Cylinders, Heads, Sectors/Track ¾ Multiple Sector Setting¾ Total Sectors Addressable in LBA Mode ¾ Translation Parameters Valid¾ Word 68 Minimum PIO transfer cycle time with Iordy ¾ Words 82-84 Features/command sets supported¾ Word 65 Minimum Multiword DMA transfer cycle time ¾ Recommended Multiword DMA transfer cycle time¾ Words 85-87 Features/command sets enabled ¾ Word 89 Time required for Security erase unit completion ¾ Word 88 Ultra DMA Modes Supported and SelectedAdditional Requirements for CF Advanced Timing Modes ¾ Word 91 Advanced power management level value¾ Word 160 Power Requirement Description ¾ Word 128 Security Status Bit 8 Security LevelTS2G~8GCF266 „ Idle 97h or E3h „ NOP 00h „ Idle Immediate 95h or E1h„ Initialize Drive Parameters 91h „ Read DMA C8h „ Read Long Sector 22h or 23h „ Read Buffer E4hTS2G~8GCF266 „ Recalibrate 1Xh „ Request Sense 03h „ Seek 7Xh „ Set Features EFh Feature Supported 266X CompactFlash Card Translate Sector Information „ Standby Immediate 94h or E0h „ Translate Sector 87h„ Wear Level F5h „ Write Buffer E8h „ Write DMA CAh TS2G~8GCF266 TS2G~8GCF266 „ Error Posting TS2G~8GCF266