Transcend Information CF 266X dimensions ¾ Device Control Register Address 3F6h376h Offset Eh

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TS2G~8GCF266

266X CompactFlash Card

¾Device Control Register (Address - 3F6h[376h]; Offset Eh)

This register is used to control the CompactFlash Storage Card interrupt request and to issue an ATA soft reset to the card. This register can be written even if the device is BUSY. The bits are defined as follows:

Bit 7: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 6: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 5: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 4: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 3: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 2 (SW Rst): this bit is set to 1 in order to force the CompactFlash Storage Card to perform an AT Disk controller Soft Reset operation. This does not change the PCMCIA Card Configuration Registers as a hardware Reset does. The Card remains in Reset until this bit is reset to ‘0.’

Bit 1 (-IEn): the Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts from the CompactFlash Storage Card are disabled. This bit also controls the Int bit in the Configuration and Status Register. This bit is set to 0 at power on and Reset.

Bit 0: this bit is ignored by the CompactFlash Storage Card.

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Contents 266X CompactFlash Card Placement FeaturesDimensions DescriptionTranscend Block Diagram Pin Assignments and Pin Type TS2G~8GCF266 Signal Description TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 Electrical Specification „ Output Drive Type „ Output Drive Characteristics „ Signal Interface „ Additional Requirements for CF Advanced Timing Modes ¾ Series termination required for Ultra DMA operation 266X CompactFlash Card„ Ultra DMA Electrical Requirements Table Typical Series Termination for Ultra DMA¾ Ultra DMA Mode Cabling Requirement „ Attribute Memory Read Timing Specification TS2G~8GCF266 „ Common Memory Read Timing Specification „ Common Memory Write Timing Specification „ I/O Input Read Timing Specification TS2G~8GCF266 „ I/O Output Write Timing Specification TS2G~8GCF266 „ True IDE PIO Mode Read/Write Timing Specification TS2G~8GCF266 „ True IDE Ultra DMA Mode Read/Write Timing Specification Table Ultra DMA Data Burst Timing266X CompactFlash Card TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 „ Multiple Function CF+ Cards Card Configuration„ Single Function CF+ Cards TS2G~8GCF266 „ Attribute Memory Function Attribute Memory FunctionTS2G~8GCF266 TS2G~8GCF266 „ Pin Replacement Register Base + 04h in Attribute Memory „ Socket and Copy Register Base + 06h in Attribute Memory Table Pcmcia Mode I/O Function Transfer FunctionCommon Memory Transfer Function Table Common Memory FunctionTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol „ I/O Primary and Secondary Address Configurations Table Primary and Secondary I/O Decoding„ Contiguous I/O Mapped Addressing Table Contiguous I/O Decoding„ True IDE Mode Addressing „ Memory Mapped Addressing„ CF-ATA Registers ¾ Data Register Address 1F0h170hOffset 0,8,9¾ Cylinder High LBA 23-16 Register Address 1F5h175h Offset ¾ Sector Count Register Address 1F2h172h Offset¾ Sector Number LBA 7-0 Register Address 1F3h173h Offset ¾ Drive/Head LBA 27-24 Register Address 1F6h176h OffsetTS2G~8GCF266 ¾ Device Control Register Address 3F6h376h Offset Eh ¾ Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set „ Check Power Mode 98h or E5h „ Execute Drive Diagnostic 90h „ Erase Sectors C0h„ Flush Cache E7h „ Format Track 50h„ Identify Device Ech 266X CompactFlash Card ¾ Word 0 General Configuration ¾ Word 6 Default Number of Sectors per Track ¾ Word 1 Default Number of Cylinders¾ Word 3 Default Number of Heads ¾ Word 49 Capabilities Bit 13 Standby Timer¾ Translation Parameters Valid ¾ Multiple Sector Setting¾ Total Sectors Addressable in LBA Mode ¾ Current Number of Cylinders, Heads, Sectors/Track¾ Recommended Multiword DMA transfer cycle time ¾ Words 82-84 Features/command sets supported¾ Word 65 Minimum Multiword DMA transfer cycle time ¾ Word 68 Minimum PIO transfer cycle time with Iordy¾ Words 85-87 Features/command sets enabled ¾ Word 88 Ultra DMA Modes Supported and Selected ¾ Word 89 Time required for Security erase unit completion¾ Word 128 Security Status Bit 8 Security Level ¾ Word 91 Advanced power management level value¾ Word 160 Power Requirement Description Additional Requirements for CF Advanced Timing ModesTS2G~8GCF266 „ Idle 97h or E3h „ NOP 00h „ Idle Immediate 95h or E1h„ Initialize Drive Parameters 91h „ Read Buffer E4h „ Read DMA C8h „ Read Long Sector 22h or 23hTS2G~8GCF266 „ Recalibrate 1Xh „ Request Sense 03h „ Seek 7Xh „ Set Features EFh Feature Supported 266X CompactFlash Card „ Standby Immediate 94h or E0h „ Translate Sector 87h Translate Sector Information„ Wear Level F5h „ Write Buffer E8h „ Write DMA CAh TS2G~8GCF266 TS2G~8GCF266 „ Error Posting TS2G~8GCF266