Section 4
Theory of Operation
Overview
This section provides the experienced technician with a thorough understanding of the ZR310 circuits and their operation. This information will aid the technician in troubleshooting the equipment.
Circuit Description
Use this detailed circuit description in conjunction with the schematic diagrams in the back of the manual.
Microprocessor
To ensure an orderly power up sequence to microprocessor U1. and its peripheral devices, the active low reset signal is not brought up until the 12 vdc supply has stabilized. Zener diodes CR5, R22/C28, and U4D accomplish this task. The delayed reset also gives crystal Y1 time to stabilize. An additional reset input comes from the long DTMF reset circuit. This circuit is a fail safe device to allow the system operator to reset the unit remotely by keying a DTMF digit for longer than 12 seconds.
Memory is functionally divided into three sections: (1) program memory, (2) operating memory, (3) protected database memory. Program memory resides in ERROR U8 and stores the actual operating instructions that make the ZR310 work as a community repeater panel. Operating memory is provided by static read/write memory RAM U3 and the internal memory in microprocessor U1. The ZR310 performs computations and maintains a data buffer in this area. Database memory contains all the user and system programming values and must be retained regardless of how often power is lost. To do this, the ZR310 stores the user and system programming values in EEPROM U5.
Peripheral timers and counters, U14 and U15 are available to the microprocessor. The counter IC's contain thee timers each which are used for tone generation and internal timing functions.
The microprocessor is able to directly control 8 I/O lines that interface to its Port 1 register on pins 13 through 20. These carry information from the various digital control outputs and inputs.
Serial Communications
Asynchronous data transfer is accomplished via a microprocessor U1's internal UART. The UART receives data through pin 11 of the microprocessor but first it is buffered to be compatible with the Motorola RIB interface via Q10/Q11/U16A. Data is transferred through pin 12 of U4 then is buffered with the same RIB interface circuit. The RIB interface baud rate is connected by the baud clock output on pin 6 of timer U15. This baud clock output is applied to the microprocessor U1 bit clock input on pin 10.
TPL/DPL Decoding
Unquenched discriminator receive audio passes through unity gain stage U18B then gets low pass filtered by U18C and U18A. This removes the voice component from the audio. The U18D and the R66/C63 filters make up a zero crossing detector, which applies the resulting digital signal to the microprocessor on pin 17. The microprocessor performs the actual decoding for the TPL tones and DPL codes using proprietary digital signal processing techniques.
DTMF Decoding
The mobile audio from the receive radio discriminator passes through unity gain stage U18B, then low pass filtered by U16C. Finally the signal is presented to the DTMF encoder/decoder U10. U12A is used to switch the audio to the DTMF decoder between receiver audio, and a DTMF telephone plugged into the programming socket J1. When a telephone (or any low impedance) is plugged into J1, U16B will sense the voltage drop across RP7D and switch the audio to the DTMF decoder.
March, 1993 | Section |