Section 4
Theory of Operation
TPL Encoding
Two signals are used for TPL generation:
•Clock frequency at the exact TPL rate from the microprocessor
•Clock frequency at 64 times the TPL rate from the timer module
These signals are fed into a switched capacitor low pass filer U17, then sent to the transmitter.
DPL Encoding
For generating DPL signals, the microprocessor sends the digital code out its pin 9. Data inversion is done inside the microprocessor if required. The timer module produces a high frequency clock signal that is fed into the low pass filter U17. Operation is very similar to TPL encoding described above.
Beep Tone Encoding
Timer U15 generates progress tones (Morse ID, warning beeps, etc). Square wave output is filtered and summed at the transmit audio junction U11D, then it passes through the output buffer amp to the transmitter audio input at
Squelch/Repeater Audio
The repeat audio is passed through input unity gain stage U18B, the audio
U12B and U12C. The microprocessor controls the squelch gate. The repeat audio is summed at the transmit audio junction U11D, then passes through the output buffer amp to the transmitter audio input at
CSQ Input
From the 8 or 16 channel GM300 radio, U4B and U4F are used to select the CSQ input connection and polarity. The COR logic signal is presented to the microprocessor input port pin 20.
March, 1993 | Section |