Philips P89LPC902, P89LPC901, P89LPC903 user manual More About Uart Mode, Sstat

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Philips Semiconductors

User’s Manual - Preliminary -

 

 

 

 

 

 

UART (P89LPC903)

P89LPC901/902/903

 

SSTAT

Address: BAh

Not bit addressable

Reset Source(s): Any reset

Reset Value: 00000000B

7

6

5

4

3

2

1

0

DBMOD

INTLO

CIDIS

DBISEL

FE

BR

OE

STINT

 

 

 

 

 

 

 

 

BIT

SYMBOL

FUNCTION

SSTAT.7

DBMOD

Double buffering mode. When set = 1 enables double buffering. Must be ’0’ for UART

 

 

mode 0. In order to be compatible with existing 80C51 devices, this bit is reset to ’0’ to

 

 

disable double buffering.

SSTAT.6

INTLO

Transmit interrupt position. When cleared = 0, the Tx interrupt is issued at the beginning

 

 

of the stop bit. When set =1, the Tx interrupt is issued at end of the stop bit. Must be ’0’

 

 

for mode 0. Note that in the case of single buffering, if the Tx interrupt occurs at the end

 

 

of a STOP bit, a gap may exist before the next start bit.

SSTAT.5

CIDIS

Combined Interrupt Disable. When set = 1, Rx and Tx interrupts are separate. When

 

 

cleared = 0, the UART uses a combined Tx/Rx interrupt (like a conventional 80C51

 

 

UART). This bit is reset to ’0’ to select combined interrupts.

SSTAT.4

DBISEL

Double buffering transmit interrupt select. Used only if double buffering is enabled.This bit

 

 

controls the number of interrupts that can occur when double buffering is enabled. When

 

 

set, one transmit interrupt is generated after each character written to SBUF, and there is

 

 

also one more transmit interrupt generated at the beginning (INTLO = 0) or the end

 

 

(INTLO = 1) of the STOP bit of the last character sent (i.e., no more data in buffer). This

 

 

last interrupt can be used to indicate that all transmit operations are over. When cleared

 

 

= 0, only one transmit interrupt is generated per character written to SBUF. Must be ’0’

 

 

when double buffering is disabled.

 

 

Note that except for the first character written (when buffer is empty), the location of the

 

 

transmit interrupt is determined by INTLO. When the first character is written, the transmit

 

 

interrupt is generated immediately after SBUF is written.

SSTAT.3

FE

Framing error flag is set when the receiver fails to see a valid STOP bit at the end of the

 

 

frame. Cleared by software.

SSTAT.2

BR

Break Detect flag. A break is detected when any 11 consecutive bits are sensed low.

 

 

Cleared by software.

SSTAT.1

OE

Overrun Error flag is set if a new character is received in the receiver buffer while it is still

 

 

full (before the software has read the previous character from the buffer), i.e., when bit 8

 

 

of a new byte is received while RI in SCON is still set. Cleared by software.

SSTAT.0

STINT

Status Interrupt Enable. When set =1, FE, BR, or OE can cause an interrupt. The

 

 

interrupt used (vector address 0023h) is shared with RI (CIDIS = 1) or the combined TI/RI

 

 

(CIDIS = 0). When cleared = 0, FE, BR, OE cannot cause an interrupt. (Note: FE, BR, or

 

 

OE is often accompanied by a RI, which will generate an interrupt regardless of the state

 

 

of STINT). Note that BR can cause a break detect reset if EBRR (AUXR1.6) is set to ’1’.

Figure 8-4: Serial Port Status Register (SSTAT)

More About UART Mode 0

In Mode 0, a write to SBUF will initiate a transmission. At the end of the transmission, TI (SCON.1) is set, which must be cleared in software. Double buffering must be disabled in this mode.

Reception is initiated by clearing RI (SCON.0). Synchronous serial transfer occurs and RI will be set again at the end of the transfer. When RI is cleared, the reception of the next character will begin. Refer to Figure 8-5 for timing.

2003 Dec 8

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Contents Philips Semiconductors User ManualTable of Contents Power Monitoring Functions 103 P89LPC901/902/903 List of Figures P89LPC902 Pin ConfigurationsProduct comparison Logic SymbolsCPU Block Diagram P89LPC901High Performance Accelerated 2-clock 80C51 CPU Block Diagram P89LPC902Uart Block Diagram P89LPC903CIN1A Mnemonic PIN no Type Name and FunctionKBI4 KBI5XTAL1 P3.1KBI0 CMP2CIN2A KBI2TxD P1.0P1.1 RxDSpecial Function Registers Table P89LPC901 Special Function RegistersBit Functions and Addresses Hex Special Function Registers Table P89LPC902 CMP1 Cmpref CIN1A KB2 KB0 KB6 KB5 KB4 A7H PRE2 PRE1 PRE0 Wdrun Wdtof Special Function Registers Table P89LPC903 F7H Psth PCH Pkbih TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Data P89LPC901/902/903 Memory OrganizationSFR CodeGeneral Description Clock Definitions Enhanced CPUCPU Clock Oscclk Low Speed Oscillator Option P89LPC901On-Chip RC oscillator Option Oscillator Option Selection- P89LPC901Clock Output P89LPC901 Watchdog Oscillator Option BIT Symbol FunctionExternal Clock Input Option P89LPC901 TrimMed freq High freqLow freq DivmAtchdog CPU Clock Cclk Modification Divm Register CPU Clock Cclk Wakeup DelayL K O sc illa to rP89LPC901/902/903 Low Power Select P89LPC901 P89LPC901/902/903 Interrupt Priority Structure Summary of Interrupts P89LPC901 Description Flag Bits Address Enable Bits Priority RankingInterrupt Arbitration Summary of Interrupts P89LPC902 DescriptionExternal Interrupt Pin Glitch Suppression P89LPC901/902/903 External Interrupt InputsTF1 ET1 TI & RI/RI ES/ESR Quasi-Bidirectional Output Configuration Port ConfigurationsNumber of I/O Pins Available Clock Source Reset Option RSTQuasi-Bidirectional Output Open Drain Output ConfigurationPort 0 Analog Functions P89LPC901/902/903 Input-Only ConfigurationPush-Pull Output Configuration Port Output Configuration P89LPC901 Additional Port FeaturesPort Output Configuration P89LPC902 Port Output Configuration P89LPC903Ports Ports TMOD.7 TmodTMOD.6 TMOD.3Tamod P89LPC901 ModeTAMOD.7-1 TAMOD.0Tcon P89LPC901/902/903 ModeMode 6 P89LPC901 Pclk Timer/Counter 0 or 1 in Mode 0 13-bit counterTR0 ENT0 Pclk TH0 Timer Overflow toggle output P89LPC901Pclk TL0 Timers 0 Real-time Clock Source Real-time clock/system timer Block DiagramFOSC2 FOSC1 FOSC0 RTCS10 Real-time Clock/System Timer Clock Source P89LPC901UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency XclkReal-time Clock/System Timer Clock Source P89LPC902/903 Reset Sources Affecting the Real-time ClockChanging RTCS1-0 Real-time Clock Interrupt/Wake UpRtccon Brownout Detection Brownout Options Power-On DetectionPower Reduction Modes P89LPC901/902/903 Power Reduction ModesPcon Pcona Power Monitoring Functions Uart P89LPC903 Baud Rate Generator and Selection P89LPC901/902/903 SFR SpaceUpdating the BRGR1 and BRGR0 SFRs SFR Locations for UARTsBrgcon Framing ErrorBreak Detect Scon Sstat More About Uart ModeSerial Port Mode 0 Double Buffering Must Be Disabled FE and RI when SM2 = 1 in Modes 2 Framing Error and RI in Modes 2 and 3 with SM2 =P89LPC901/902/903 More About Uart Modes 2 PCON.6 RB8 SMOD0Double Buffering in Different Modes P89LPC901/902/903 Double BufferingTransmission with and without Double Buffering 9th Bit Bit 8 in Double Buffering Modes 1, 2Automatic Address Recognition Multiprocessor CommunicationsUart P89LPC903 Uart P89LPC903 Block Diagram of Reset Power-On reset code executionRstsrc CMPn Comparator ConfigurationComparator Input and Output Connections P89LPC901 Cmpref Internal Reference VoltageComparator Interrupt Comparator Configuration Example Comparator and Power Reduction ModesKBPATN.5,4 KbpatnKbmask KbconKBMASK.6 KBMASK.7KBMASK.3 KBMASK.2Keypad Interrupt KBI Wdte Wdse Function Watchdog timer configurationWatchdog Function Feed Sequence Wdcon WDCONA7H P89LPC901/902/903 Watchdog Timeout ValuesPrescaler Reset Pclk Power down operation P89LPC901/902/903 Watchdog Timer in Timer ModeWatchdog Clock Source PrescalerWatchdog Timer Watchdog Timer Watchdog Timer AUXR1 Software ResetDual Data Pointers MOVX@DPTR, a MOVCA, @A+DPTRMOVXA, @DPTR Using Flash as data storage FeaturesGeneral description Introduction to IAP-LiteFlash Program Memory Fmcon C-language routine to erase/program all or part of a Accessing additional flash elementsUCFG1 Erase-programming additional flash elementsReading additional flash elements Fmadrl C-language routine to read a flash element User Configuration BytesP89LPC901 UCFG1SECx User Security BytesBoot Status P89LPC901/902/903 Boot VectorBootvec BootstatLogical ArithmeticData Transfer Mnemonic Description Bytes Cycles Hex CodeBranching BooleanB8-BF RetiD8-DF MiscellaneousRevision History 108 Index Dual Data Pointers Port 0 12, 14 SFR 113 P89LPC901/902/903

P89LPC903, P89LPC902, P89LPC901 specifications

The Philips P89LPC901, P89LPC902, and P89LPC903 are a series of 8-bit microcontrollers designed for embedded system applications. These models, which belong to the LPC900 series, are notable for their affordability and versatility, making them an attractive choice for both hobbyists and professional developers.

One of the core features of the P89LPC901, P89LPC902, and P89LPC903 microcontrollers is their powerful 8-bit architecture. Operating at clock speeds up to 20 MHz, they deliver efficient performance suited for a range of tasks. Each model includes a comprehensive instruction set that supports various data manipulation and arithmetic functions, enabling extensive programming capabilities.

These microcontrollers come with built-in memory, with configurations that vary among the three models. The P89LPC901 typically features 4 KB of Flash memory and 256 bytes of RAM, while the P89LPC902 and P89LPC903 offer enhanced memory options. This Flash memory allows for reprogrammability, making it easier to update and modify applications as needed.

Another significant characteristic of the LPC900 series is their integrated peripherals. These models are equipped with a variety of I/O ports, allowing for easy interfacing with other devices and components. The P89LPC901 supports up to 32 I/O pins, while the P89LPC902 and P89LPC903 provide additional features such as analog-to-digital converters (ADCs), timers, and serial communication interfaces. This broad range of peripherals empowers developers to design complex applications without needing extra hardware.

Power consumption is also a key consideration for microcontroller applications. The P89LPC901, P89LPC902, and P89LPC903 are designed with low power consumption in mind, making them ideal for battery-operated devices and energy-efficient projects. They can operate in various power modes, allowing for greater flexibility in deployment.

In terms of technology, these microcontrollers utilize advanced CMOS technology, ensuring high reliability and durability. Their design offers a robust solution for numerous applications, including consumer electronics, industrial controls, and automation systems.

In summary, the Philips P89LPC901, P89LPC902, and P89LPC903 microcontrollers present an attractive combination of performance, integrated peripherals, low power consumption, and versatility. Their features cater to a wide array of applications, keeping them relevant in a rapidly evolving technology landscape. For hobbyists and professionals alike, these microcontrollers represent a reliable foundation for embedded system development.
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