Philips P89LPC902, P89LPC901 Watchdog Function, Watchdog timer configuration, Wdte Wdse Function

Page 83

 

Philips Semiconductors

User’s Manual - Preliminary -

 

 

 

 

 

 

WATCHDOG TIMER

P89LPC901/902/903

 

 

12. WATCHDOG TIMER

 

 

The watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when it underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count. The watchdog timer can only be reset by a power-on reset.

Watchdog Function

The user has the ability using the WDCON and UCFG1 registers to control the run /stop condition of the WDT, the clock source for the WDT, the prescaler value, and whether the WDT is enabled to reset the device on underflow. In addition, there is a safety mechanism which forces the WDT to be enabled by values programmed into UCFG1 either through IAP or a commercial programmer.

The WDTE bit (UCFG1.7), if set, enables the WDT to reset the device on underflow. Following reset, the WDT will be running regardless of the state of the WDTE bit.

The WDRUN bit (WDCON.2) can be set to start the WDT and cleared to stop the WDT. Following reset this bit will be set and the WDT will be running. All writes to WDCON need to be followed by a feed sequence (see section "Feed Sequence" on page 84). Additional bits in WDCON allow the user to select the clocksource for the WDT and the prescaler.

When the timer is not enabled to reset the device on underflow, the WDT can be used in "timer mode" and be enabled to produce an interrupt (IEN0.6) if desired.

The Watchdog Safety Enable bit, WDSE (UCFG1.4) along with WDTE, is designed to force certain operating conditions at power- up. Refer to the Table for details.

Table 12-1: Watchdog timer configuration

WDTE

WDSE

 

FUNCTION

(UCFG1.7)

(UCFG1.4)

 

 

 

 

 

 

0

x

The watchdog reset is disabled. The timer can be used as an internal timer and

can be used to generate an interrupt. WDSE has no effect.

 

 

 

 

 

1

0

The watchdog reset is enabled. The user can set WDCLK to choose the clock

source.

 

 

 

 

 

 

 

The watchdog reset is enabled, along with additional safety features:

1

1

1.

WDCLK is forced to 1 (using watchdog oscillator)

2.

WDCON and WDL register can only be written once

 

 

 

 

3.

WDRUN is forced to 1and cannot be cleared by software.

 

 

 

 

Figure 12-3 shows the watchdog timer in watchdog mode. It consists of a programmable 13-bit prescaler, and an 8-bit down counter. The down counter is clocked (decremented) by a tap taken from the prescaler. The clock source for the prescaler is either PCLK or the watchdog oscillator selected by the WDCLK bit in the WDCON register. (Note that switching of the clock sources will not take effect immediately - see section "Watchdog Clock Source" on page 87).

The watchdog asserts the watchdog reset when the watchdog count underflows and the watchdog reset is enabled. When the watchdog reset is enabled, writing to WDL or WDCON must be followed by a feed sequence for the new values to take effect.

If a watchdog reset occurs, the internal reset is active for at least one watchdog clock cycle (PCLK or the watchdog oscillator clock). If CCLK is still running, code execution will begin immediately after the reset cycle. If the processor was in Power down mode, the watchdog reset will start the oscillator and code execution will resume after the oscillator is stable.

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Contents Philips Semiconductors User ManualTable of Contents Power Monitoring Functions 103 P89LPC901/902/903 List of Figures P89LPC902 Pin ConfigurationsProduct comparison Logic SymbolsCPU Block Diagram P89LPC901High Performance Accelerated 2-clock 80C51 CPU Block Diagram P89LPC902Uart Block Diagram P89LPC903KBI5 Mnemonic PIN no Type Name and FunctionCIN1A KBI4XTAL1 P3.1KBI2 CMP2KBI0 CIN2ARxD P1.0TxD P1.1Special Function Registers Table P89LPC901 Special Function RegistersBit Functions and Addresses Hex Special Function Registers Table P89LPC902 CMP1 Cmpref CIN1A KB2 KB0 KB6 KB5 KB4 A7H PRE2 PRE1 PRE0 Wdrun Wdtof Special Function Registers Table P89LPC903 F7H Psth PCH Pkbih TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Code P89LPC901/902/903 Memory OrganizationData SFRGeneral Description Low Speed Oscillator Option P89LPC901 Enhanced CPUClock Definitions CPU Clock OscclkOn-Chip RC oscillator Option Oscillator Option Selection- P89LPC901Clock Output P89LPC901 Trim BIT Symbol FunctionWatchdog Oscillator Option External Clock Input Option P89LPC901Divm High freqMed freq Low freqAtchdog O sc illa to r CPU Clock Cclk Wakeup DelayCPU Clock Cclk Modification Divm Register L KP89LPC901/902/903 Low Power Select P89LPC901 P89LPC901/902/903 Interrupt Priority Structure Summary of Interrupts P89LPC902 Description Flag Bits Address Enable Bits Priority RankingSummary of Interrupts P89LPC901 Description Interrupt ArbitrationExternal Interrupt Pin Glitch Suppression P89LPC901/902/903 External Interrupt InputsTF1 ET1 TI & RI/RI ES/ESR RST Port ConfigurationsQuasi-Bidirectional Output Configuration Number of I/O Pins Available Clock Source Reset OptionQuasi-Bidirectional Output Open Drain Output ConfigurationPort 0 Analog Functions P89LPC901/902/903 Input-Only ConfigurationPush-Pull Output Configuration Port Output Configuration P89LPC903 Additional Port FeaturesPort Output Configuration P89LPC901 Port Output Configuration P89LPC902Ports Ports TMOD.3 TmodTMOD.7 TMOD.6TAMOD.0 ModeTamod P89LPC901 TAMOD.7-1Tcon P89LPC901/902/903 ModeMode 6 P89LPC901 Pclk Timer/Counter 0 or 1 in Mode 0 13-bit counterTR0 ENT0 Pclk TH0 Timer Overflow toggle output P89LPC901Pclk TL0 Timers 0 Real-time Clock Source Real-time clock/system timer Block DiagramXclk Real-time Clock/System Timer Clock Source P89LPC901FOSC2 FOSC1 FOSC0 RTCS10 UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock FrequencyReal-time Clock Interrupt/Wake Up Reset Sources Affecting the Real-time ClockReal-time Clock/System Timer Clock Source P89LPC902/903 Changing RTCS1-0Rtccon Brownout Detection Brownout Options Power-On DetectionPower Reduction Modes P89LPC901/902/903 Power Reduction ModesPcon Pcona Power Monitoring Functions Uart P89LPC903 SFR Locations for UARTs P89LPC901/902/903 SFR SpaceBaud Rate Generator and Selection Updating the BRGR1 and BRGR0 SFRsBrgcon Framing ErrorBreak Detect Scon Sstat More About Uart ModeSerial Port Mode 0 Double Buffering Must Be Disabled PCON.6 RB8 SMOD0 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 P89LPC901/902/903 More About Uart Modes 2Double Buffering in Different Modes P89LPC901/902/903 Double BufferingTransmission with and without Double Buffering 9th Bit Bit 8 in Double Buffering Modes 1, 2Automatic Address Recognition Multiprocessor CommunicationsUart P89LPC903 Uart P89LPC903 Block Diagram of Reset Power-On reset code executionRstsrc CMPn Comparator ConfigurationComparator Input and Output Connections P89LPC901 Cmpref Internal Reference VoltageComparator Interrupt Comparator Configuration Example Comparator and Power Reduction ModesKBPATN.5,4 KbpatnKbmask KbconKBMASK.2 KBMASK.7KBMASK.6 KBMASK.3Keypad Interrupt KBI Wdte Wdse Function Watchdog timer configurationWatchdog Function Feed Sequence Wdcon WDCONA7H P89LPC901/902/903 Watchdog Timeout ValuesPrescaler Reset Pclk Prescaler P89LPC901/902/903 Watchdog Timer in Timer ModePower down operation Watchdog Clock SourceWatchdog Timer Watchdog Timer Watchdog Timer AUXR1 Software ResetDual Data Pointers MOVX@DPTR, a MOVCA, @A+DPTRMOVXA, @DPTR Introduction to IAP-Lite FeaturesUsing Flash as data storage General descriptionFlash Program Memory Fmcon C-language routine to erase/program all or part of a Accessing additional flash elementsUCFG1 Erase-programming additional flash elementsReading additional flash elements Fmadrl C-language routine to read a flash element User Configuration BytesP89LPC901 UCFG1SECx User Security BytesBootstat P89LPC901/902/903 Boot VectorBoot Status BootvecLogical ArithmeticData Transfer Mnemonic Description Bytes Cycles Hex CodeBranching BooleanMiscellaneous RetiB8-BF D8-DFRevision History 108 Index Dual Data Pointers Port 0 12, 14 SFR 113 P89LPC901/902/903

P89LPC903, P89LPC902, P89LPC901 specifications

The Philips P89LPC901, P89LPC902, and P89LPC903 are a series of 8-bit microcontrollers designed for embedded system applications. These models, which belong to the LPC900 series, are notable for their affordability and versatility, making them an attractive choice for both hobbyists and professional developers.

One of the core features of the P89LPC901, P89LPC902, and P89LPC903 microcontrollers is their powerful 8-bit architecture. Operating at clock speeds up to 20 MHz, they deliver efficient performance suited for a range of tasks. Each model includes a comprehensive instruction set that supports various data manipulation and arithmetic functions, enabling extensive programming capabilities.

These microcontrollers come with built-in memory, with configurations that vary among the three models. The P89LPC901 typically features 4 KB of Flash memory and 256 bytes of RAM, while the P89LPC902 and P89LPC903 offer enhanced memory options. This Flash memory allows for reprogrammability, making it easier to update and modify applications as needed.

Another significant characteristic of the LPC900 series is their integrated peripherals. These models are equipped with a variety of I/O ports, allowing for easy interfacing with other devices and components. The P89LPC901 supports up to 32 I/O pins, while the P89LPC902 and P89LPC903 provide additional features such as analog-to-digital converters (ADCs), timers, and serial communication interfaces. This broad range of peripherals empowers developers to design complex applications without needing extra hardware.

Power consumption is also a key consideration for microcontroller applications. The P89LPC901, P89LPC902, and P89LPC903 are designed with low power consumption in mind, making them ideal for battery-operated devices and energy-efficient projects. They can operate in various power modes, allowing for greater flexibility in deployment.

In terms of technology, these microcontrollers utilize advanced CMOS technology, ensuring high reliability and durability. Their design offers a robust solution for numerous applications, including consumer electronics, industrial controls, and automation systems.

In summary, the Philips P89LPC901, P89LPC902, and P89LPC903 microcontrollers present an attractive combination of performance, integrated peripherals, low power consumption, and versatility. Their features cater to a wide array of applications, keeping them relevant in a rapidly evolving technology landscape. For hobbyists and professionals alike, these microcontrollers represent a reliable foundation for embedded system development.
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