Philips P89LPC903, P89LPC901 Multiprocessor Communications, Automatic Address Recognition

Page 70

 

Philips Semiconductors

User’s Manual - Preliminary -

 

 

 

 

 

 

UART (P89LPC903)

P89LPC901/902/903

 

-If DBISEL is ’1’ and INTLO is ’1’, a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter (which is also the last data).

7.If there is more data, the CPU writes to TB8 again.

8.The CPU writes to SBUF again. Then:

-If INTLO is ’0’, the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data cur- rently in the shifter.

-If INTLO is ’1’, the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter.

Go to 4.

Note that if DBISEL is ’1’ and the CPU is writing to SBUF when the STOP bit of the last data is shifted out, there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following.

Multiprocessor Communications

UART modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received or transmitted. When data is received, the 9th bit is stored in RB8. The UART can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit SM2 in SCON. One way to use this feature in multiprocessor systems is as follows:

When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that follow. The slaves that weren’t being addressed leave their SM2 bits set and go on about their business, ignoring the subsequent data bytes.

Note that SM2 has no effect in Mode 0, and must be ’0’ in Mode 1.

Automatic Address Recognition

Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes (mode 2 and mode 3), the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data.

Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme:

Slave 0

SADDR = 1100

0000

 

SADEN = 1111

1101

 

Given

= 1100

00X0

Slave 1

SADDR = 1100

0000

 

SADEN = 1111

1110

 

Given

= 1100

000X

In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010

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Contents User Manual Philips SemiconductorsTable of Contents Power Monitoring Functions 103 P89LPC901/902/903 List of Figures Pin Configurations P89LPC902Logic Symbols Product comparisonBlock Diagram P89LPC901 CPUBlock Diagram P89LPC902 High Performance Accelerated 2-clock 80C51 CPUBlock Diagram P89LPC903 UartKBI4 Mnemonic PIN no Type Name and FunctionCIN1A KBI5P3.1 XTAL1CIN2A CMP2KBI0 KBI2P1.1 P1.0TxD RxDSpecial Function Registers Special Function Registers Table P89LPC901Bit Functions and Addresses Hex Special Function Registers Table P89LPC902 CMP1 Cmpref CIN1A KB2 KB0 KB6 KB5 KB4 A7H PRE2 PRE1 PRE0 Wdrun Wdtof Special Function Registers Table P89LPC903 F7H Psth PCH Pkbih TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# SFR P89LPC901/902/903 Memory OrganizationData CodeGeneral Description CPU Clock Oscclk Enhanced CPUClock Definitions Low Speed Oscillator Option P89LPC901Clock Output P89LPC901 Oscillator Option Selection- P89LPC901On-Chip RC oscillator Option External Clock Input Option P89LPC901 BIT Symbol FunctionWatchdog Oscillator Option TrimLow freq High freqMed freq DivmAtchdog L K CPU Clock Cclk Wakeup DelayCPU Clock Cclk Modification Divm Register O sc illa to rP89LPC901/902/903 Low Power Select P89LPC901 P89LPC901/902/903 Interrupt Priority Structure Interrupt Arbitration Flag Bits Address Enable Bits Priority RankingSummary of Interrupts P89LPC901 Description Summary of Interrupts P89LPC902 DescriptionP89LPC901/902/903 External Interrupt Inputs External Interrupt Pin Glitch SuppressionTF1 ET1 TI & RI/RI ES/ESR Number of I/O Pins Available Clock Source Reset Option Port ConfigurationsQuasi-Bidirectional Output Configuration RSTOpen Drain Output Configuration Quasi-Bidirectional OutputPush-Pull Output Configuration P89LPC901/902/903 Input-Only ConfigurationPort 0 Analog Functions Port Output Configuration P89LPC902 Additional Port FeaturesPort Output Configuration P89LPC901 Port Output Configuration P89LPC903Ports Ports TMOD.6 TmodTMOD.7 TMOD.3TAMOD.7-1 ModeTamod P89LPC901 TAMOD.0Mode 6 P89LPC901 P89LPC901/902/903 ModeTcon Timer/Counter 0 or 1 in Mode 0 13-bit counter PclkPclk TL0 Timer Overflow toggle output P89LPC901TR0 ENT0 Pclk TH0 Timers 0 Real-time clock/system timer Block Diagram Real-time Clock SourceUCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency Real-time Clock/System Timer Clock Source P89LPC901FOSC2 FOSC1 FOSC0 RTCS10 XclkChanging RTCS1-0 Reset Sources Affecting the Real-time ClockReal-time Clock/System Timer Clock Source P89LPC902/903 Real-time Clock Interrupt/Wake UpRtccon Brownout Detection Power-On Detection Brownout OptionsP89LPC901/902/903 Power Reduction Modes Power Reduction ModesPcon Pcona Power Monitoring Functions Uart P89LPC903 Updating the BRGR1 and BRGR0 SFRs P89LPC901/902/903 SFR SpaceBaud Rate Generator and Selection SFR Locations for UARTsBreak Detect Framing ErrorBrgcon Scon More About Uart Mode SstatSerial Port Mode 0 Double Buffering Must Be Disabled P89LPC901/902/903 More About Uart Modes 2 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 PCON.6 RB8 SMOD0P89LPC901/902/903 Double Buffering Double Buffering in Different Modes9th Bit Bit 8 in Double Buffering Modes 1, 2 Transmission with and without Double BufferingMultiprocessor Communications Automatic Address RecognitionUart P89LPC903 Uart P89LPC903 Power-On reset code execution Block Diagram of ResetRstsrc Comparator Configuration CMPnComparator Input and Output Connections P89LPC901 Comparator Interrupt Internal Reference VoltageCmpref Comparator and Power Reduction Modes Comparator Configuration ExampleKbpatn KBPATN.5,4Kbcon KbmaskKBMASK.3 KBMASK.7KBMASK.6 KBMASK.2Keypad Interrupt KBI Watchdog Function Watchdog timer configurationWdte Wdse Function Feed Sequence Wdcon Prescaler Reset Pclk P89LPC901/902/903 Watchdog Timeout ValuesWDCONA7H Watchdog Clock Source P89LPC901/902/903 Watchdog Timer in Timer ModePower down operation PrescalerWatchdog Timer Watchdog Timer Watchdog Timer Dual Data Pointers Software ResetAUXR1 MOVXA, @DPTR MOVCA, @A+DPTRMOVX@DPTR, a General description FeaturesUsing Flash as data storage Introduction to IAP-LiteFlash Program Memory Fmcon Accessing additional flash elements C-language routine to erase/program all or part of aReading additional flash elements Erase-programming additional flash elementsUCFG1 Fmadrl User Configuration Bytes C-language routine to read a flash elementUCFG1 P89LPC901User Security Bytes SECxBootvec P89LPC901/902/903 Boot VectorBoot Status BootstatArithmetic LogicalMnemonic Description Bytes Cycles Hex Code Data TransferBoolean BranchingD8-DF RetiB8-BF MiscellaneousRevision History 108 Index Dual Data Pointers Port 0 12, 14 SFR 113 P89LPC901/902/903

P89LPC903, P89LPC902, P89LPC901 specifications

The Philips P89LPC901, P89LPC902, and P89LPC903 are a series of 8-bit microcontrollers designed for embedded system applications. These models, which belong to the LPC900 series, are notable for their affordability and versatility, making them an attractive choice for both hobbyists and professional developers.

One of the core features of the P89LPC901, P89LPC902, and P89LPC903 microcontrollers is their powerful 8-bit architecture. Operating at clock speeds up to 20 MHz, they deliver efficient performance suited for a range of tasks. Each model includes a comprehensive instruction set that supports various data manipulation and arithmetic functions, enabling extensive programming capabilities.

These microcontrollers come with built-in memory, with configurations that vary among the three models. The P89LPC901 typically features 4 KB of Flash memory and 256 bytes of RAM, while the P89LPC902 and P89LPC903 offer enhanced memory options. This Flash memory allows for reprogrammability, making it easier to update and modify applications as needed.

Another significant characteristic of the LPC900 series is their integrated peripherals. These models are equipped with a variety of I/O ports, allowing for easy interfacing with other devices and components. The P89LPC901 supports up to 32 I/O pins, while the P89LPC902 and P89LPC903 provide additional features such as analog-to-digital converters (ADCs), timers, and serial communication interfaces. This broad range of peripherals empowers developers to design complex applications without needing extra hardware.

Power consumption is also a key consideration for microcontroller applications. The P89LPC901, P89LPC902, and P89LPC903 are designed with low power consumption in mind, making them ideal for battery-operated devices and energy-efficient projects. They can operate in various power modes, allowing for greater flexibility in deployment.

In terms of technology, these microcontrollers utilize advanced CMOS technology, ensuring high reliability and durability. Their design offers a robust solution for numerous applications, including consumer electronics, industrial controls, and automation systems.

In summary, the Philips P89LPC901, P89LPC902, and P89LPC903 microcontrollers present an attractive combination of performance, integrated peripherals, low power consumption, and versatility. Their features cater to a wide array of applications, keeping them relevant in a rapidly evolving technology landscape. For hobbyists and professionals alike, these microcontrollers represent a reliable foundation for embedded system development.
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