Philips P89LPC903, P89LPC901, P89LPC902 user manual Software Reset, Dual Data Pointers, AUXR1

Page 91

 

Philips Semiconductors

User’s Manual - Preliminary -

 

 

 

 

 

 

ADDITIONAL FEATURES

P89LPC901/902/903

 

 

13. ADDITIONAL FEATURES

 

 

The AUXR1 register contains several special purpose control bits that relate to several chip features. AUXR1 is described in Figure 13-1.

AUXR1

 

7

6

5

 

4

 

3

 

2

1

0

 

Address: A2h

 

 

CLKLP

EBRR

-

 

-

 

SRST

 

0

-

DPS

 

Not bit addressable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset Source(s): Any reset

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset Value: 000000x0B

 

 

 

 

 

 

 

 

 

 

 

 

 

BIT

SYMBOL

FUNCTION

 

 

 

 

 

 

 

 

 

 

 

AUXR1.7

CLKLP

Clock Low Power Select. When set, reduces power consumption in the clock circuits. Can

 

 

be used when the clock frequency is 8MHz or less. After reset this bit is cleared to support

 

 

up to 12MHz operation (P89LPC901).

 

 

 

 

 

 

AUXR1.6

EBRR

UART Break Detect Reset Enable. If ’1’, UART Break Detect will cause a chip reset

 

 

(P89LPC903). When writing to this register on the P89LPC901 or P89LPC902 devices,

 

 

this bit position should be written with a zero.

 

 

 

 

 

 

AUXR1.5

-

Reserved

 

 

 

 

 

 

 

 

 

 

 

AUXR1.4

-

Reserved

 

 

 

 

 

 

 

 

 

 

 

AUXR1.3

SRST

Software Reset. When set by software, resets the P89LPC901/902/903 as if a hardware

 

 

reset occurred.

 

 

 

 

 

 

 

 

 

 

AUXR1.2

0

This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing AUXR1,

 

 

without interfering with other bits in the register.

 

 

 

 

AUXR1.1

-

Not used. Allowable to set to a "1" .

 

 

 

 

 

 

 

 

AUXR1.0

DPS

Data Pointer Select. Chooses one of two Data Pointers.

 

 

 

 

Figure 13-1: AUXR1 Register

Software Reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. If a value is written to AUXR1 that contains a 1 at bit position 3, all SFRs will be initialized and execution will resume at program address 0000. Care should be taken when writing to AUXR1 to avoid accidental software resets.

Dual Data Pointers

The dual Data Pointers (DPTR) adds to the ways in which the processor can specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. The DPTR that is not currently selected is not accessible to software unless the DPS bit is toggled.

Specific instructions affected by the Data Pointer selection are:

•

INC

DPTR

Increments the Data Pointer by 1.

•

JMP

@A+DPTR

Jump indirect relative to DPTR value.

2003 Dec 8

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Contents Philips Semiconductors User ManualTable of Contents Power Monitoring Functions 103 P89LPC901/902/903 List of Figures P89LPC902 Pin ConfigurationsProduct comparison Logic SymbolsCPU Block Diagram P89LPC901High Performance Accelerated 2-clock 80C51 CPU Block Diagram P89LPC902Uart Block Diagram P89LPC903KBI5 Mnemonic PIN no Type Name and FunctionCIN1A KBI4XTAL1 P3.1KBI2 CMP2KBI0 CIN2ARxD P1.0TxD P1.1Special Function Registers Table P89LPC901 Special Function RegistersBit Functions and Addresses Hex Special Function Registers Table P89LPC902 CMP1 Cmpref CIN1A KB2 KB0 KB6 KB5 KB4 A7H PRE2 PRE1 PRE0 Wdrun Wdtof Special Function Registers Table P89LPC903 F7H Psth PCH Pkbih TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Code P89LPC901/902/903 Memory OrganizationData SFRGeneral Description Low Speed Oscillator Option P89LPC901 Enhanced CPUClock Definitions CPU Clock OscclkClock Output P89LPC901 Oscillator Option Selection- P89LPC901On-Chip RC oscillator Option Trim BIT Symbol FunctionWatchdog Oscillator Option External Clock Input Option P89LPC901Divm High freqMed freq Low freqAtchdog O sc illa to r CPU Clock Cclk Wakeup DelayCPU Clock Cclk Modification Divm Register L KP89LPC901/902/903 Low Power Select P89LPC901 P89LPC901/902/903 Interrupt Priority Structure Summary of Interrupts P89LPC902 Description Flag Bits Address Enable Bits Priority RankingSummary of Interrupts P89LPC901 Description Interrupt ArbitrationExternal Interrupt Pin Glitch Suppression P89LPC901/902/903 External Interrupt InputsTF1 ET1 TI & RI/RI ES/ESR RST Port ConfigurationsQuasi-Bidirectional Output Configuration Number of I/O Pins Available Clock Source Reset OptionQuasi-Bidirectional Output Open Drain Output ConfigurationPush-Pull Output Configuration P89LPC901/902/903 Input-Only ConfigurationPort 0 Analog Functions Port Output Configuration P89LPC903 Additional Port FeaturesPort Output Configuration P89LPC901 Port Output Configuration P89LPC902Ports Ports TMOD.3 TmodTMOD.7 TMOD.6TAMOD.0 ModeTamod P89LPC901 TAMOD.7-1Mode 6 P89LPC901 P89LPC901/902/903 ModeTcon Pclk Timer/Counter 0 or 1 in Mode 0 13-bit counterPclk TL0 Timer Overflow toggle output P89LPC901TR0 ENT0 Pclk TH0 Timers 0 Real-time Clock Source Real-time clock/system timer Block DiagramXclk Real-time Clock/System Timer Clock Source P89LPC901FOSC2 FOSC1 FOSC0 RTCS10 UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock FrequencyReal-time Clock Interrupt/Wake Up Reset Sources Affecting the Real-time ClockReal-time Clock/System Timer Clock Source P89LPC902/903 Changing RTCS1-0Rtccon Brownout Detection Brownout Options Power-On DetectionPower Reduction Modes P89LPC901/902/903 Power Reduction ModesPcon Pcona Power Monitoring Functions Uart P89LPC903 SFR Locations for UARTs P89LPC901/902/903 SFR SpaceBaud Rate Generator and Selection Updating the BRGR1 and BRGR0 SFRsBreak Detect Framing ErrorBrgcon Scon Sstat More About Uart ModeSerial Port Mode 0 Double Buffering Must Be Disabled PCON.6 RB8 SMOD0 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 P89LPC901/902/903 More About Uart Modes 2Double Buffering in Different Modes P89LPC901/902/903 Double BufferingTransmission with and without Double Buffering 9th Bit Bit 8 in Double Buffering Modes 1, 2Automatic Address Recognition Multiprocessor CommunicationsUart P89LPC903 Uart P89LPC903 Block Diagram of Reset Power-On reset code executionRstsrc CMPn Comparator ConfigurationComparator Input and Output Connections P89LPC901 Comparator Interrupt Internal Reference VoltageCmpref Comparator Configuration Example Comparator and Power Reduction ModesKBPATN.5,4 KbpatnKbmask KbconKBMASK.2 KBMASK.7KBMASK.6 KBMASK.3Keypad Interrupt KBI Watchdog Function Watchdog timer configurationWdte Wdse Function Feed Sequence Wdcon Prescaler Reset Pclk P89LPC901/902/903 Watchdog Timeout ValuesWDCONA7H Prescaler P89LPC901/902/903 Watchdog Timer in Timer ModePower down operation Watchdog Clock SourceWatchdog Timer Watchdog Timer Watchdog Timer Dual Data Pointers Software ResetAUXR1 MOVXA, @DPTR MOVCA, @A+DPTRMOVX@DPTR, a Introduction to IAP-Lite FeaturesUsing Flash as data storage General descriptionFlash Program Memory Fmcon C-language routine to erase/program all or part of a Accessing additional flash elementsReading additional flash elements Erase-programming additional flash elementsUCFG1 Fmadrl C-language routine to read a flash element User Configuration BytesP89LPC901 UCFG1SECx User Security BytesBootstat P89LPC901/902/903 Boot VectorBoot Status BootvecLogical ArithmeticData Transfer Mnemonic Description Bytes Cycles Hex CodeBranching BooleanMiscellaneous RetiB8-BF D8-DFRevision History 108 Index Dual Data Pointers Port 0 12, 14 SFR 113 P89LPC901/902/903

P89LPC903, P89LPC902, P89LPC901 specifications

The Philips P89LPC901, P89LPC902, and P89LPC903 are a series of 8-bit microcontrollers designed for embedded system applications. These models, which belong to the LPC900 series, are notable for their affordability and versatility, making them an attractive choice for both hobbyists and professional developers.

One of the core features of the P89LPC901, P89LPC902, and P89LPC903 microcontrollers is their powerful 8-bit architecture. Operating at clock speeds up to 20 MHz, they deliver efficient performance suited for a range of tasks. Each model includes a comprehensive instruction set that supports various data manipulation and arithmetic functions, enabling extensive programming capabilities.

These microcontrollers come with built-in memory, with configurations that vary among the three models. The P89LPC901 typically features 4 KB of Flash memory and 256 bytes of RAM, while the P89LPC902 and P89LPC903 offer enhanced memory options. This Flash memory allows for reprogrammability, making it easier to update and modify applications as needed.

Another significant characteristic of the LPC900 series is their integrated peripherals. These models are equipped with a variety of I/O ports, allowing for easy interfacing with other devices and components. The P89LPC901 supports up to 32 I/O pins, while the P89LPC902 and P89LPC903 provide additional features such as analog-to-digital converters (ADCs), timers, and serial communication interfaces. This broad range of peripherals empowers developers to design complex applications without needing extra hardware.

Power consumption is also a key consideration for microcontroller applications. The P89LPC901, P89LPC902, and P89LPC903 are designed with low power consumption in mind, making them ideal for battery-operated devices and energy-efficient projects. They can operate in various power modes, allowing for greater flexibility in deployment.

In terms of technology, these microcontrollers utilize advanced CMOS technology, ensuring high reliability and durability. Their design offers a robust solution for numerous applications, including consumer electronics, industrial controls, and automation systems.

In summary, the Philips P89LPC901, P89LPC902, and P89LPC903 microcontrollers present an attractive combination of performance, integrated peripherals, low power consumption, and versatility. Their features cater to a wide array of applications, keeping them relevant in a rapidly evolving technology landscape. For hobbyists and professionals alike, these microcontrollers represent a reliable foundation for embedded system development.
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