Philips P89LPC903, P89LPC901, P89LPC902 user manual Scon

Page 64

 

Philips Semiconductors

User’s Manual - Preliminary -

 

 

 

 

 

 

UART (P89LPC903)

P89LPC901/902/903

 

.

SCON

Address: 98h Bit addressable

Reset Source(s): Any reset

Reset Value: 00000000B

7

6

5

4

3

2

1

0

SM0/FE

SM1

SM2

REN

TB8

RB8

TI

RI

 

 

 

 

 

 

 

 

BIT

SYMBOL

FUNCTION

 

SCON.7

SM0/FE

The use of this bit is determined by SMOD0 in the PCON register. If SMOD0 = 0, this bit

 

 

is read and written as SM0, which with SM1, defines the serial port mode. If SMOD0 = 1,

 

 

this bit is read and written as FE (Framing Error). FE is set by the receiver when an invalid

 

 

stop bit is detected. Once set, this bit cannot be cleared by valid frames but is cleared by

 

 

software. (Note: UART mode bits SM0 and SM1 should be programmed when SMOD0 is

 

 

’0’ - default mode on any reset.)

SCON. 6

SM1

With SM0, defines the serial port mode (see table below).

 

SM0, SM1

UART Mode

UART 0 Baud Rate

 

0 0

0: shift register

CCLK/16 (default mode on any reset)

 

0 1

1: 8-bit UART

Variable (see Table )

 

1 0

2: 9-bit UART

CCLK/32 or CCLK/16

 

1 1

3: 9-bit UART

Variable (see Table )

SCON.5

SM2

Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or 3, if

 

 

SM2 is set to 1, then Rl will not be activated if the received 9th data bit (RB8) is 0. In Mode

 

 

0, SM2 should be 0. In Mode 1, SM2 must be 0.

SCON.4

REN

Enables serial reception. Set by software to enable reception. Clear by software to disable

 

 

reception.

 

SCON.3

TB8

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as

 

 

desired.

 

SCON.2

RB8

The 9th data bit that was received in Modes 2 and 3. In Mode 1 (SM2 must be 0), RB8 is

 

 

the stop bit that was received. In Mode 0, RB8 is undefined.

SCON.1

TI

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the

 

 

the stop bit (see description of INTLO bit in SSTAT register) in the other modes. Must be

 

 

cleared by software.

SCON.0

RI

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or

 

 

approximately halfway through the stop bit time in Mode 1. For Mode 2 or Mode 3, if

SMOD0, it is set near the middle of the 9th data bit (bit 8). If SMOD0 = 1, it is set near the middle of the stop bit (see SM2 - SCON.5 - for exceptions). Must be cleared by software.

Figure 8-3: Serial Port Control Register (SCON)

2003 Dec 8

64

Image 64
Contents User Manual Philips SemiconductorsTable of Contents Power Monitoring Functions 103 P89LPC901/902/903 List of Figures Pin Configurations P89LPC902Logic Symbols Product comparisonBlock Diagram P89LPC901 CPUBlock Diagram P89LPC902 High Performance Accelerated 2-clock 80C51 CPUBlock Diagram P89LPC903 UartMnemonic PIN no Type Name and Function CIN1AKBI4 KBI5P3.1 XTAL1CMP2 KBI0CIN2A KBI2P1.0 TxDP1.1 RxDSpecial Function Registers Special Function Registers Table P89LPC901Bit Functions and Addresses Hex Special Function Registers Table P89LPC902 CMP1 Cmpref CIN1A KB2 KB0 KB6 KB5 KB4 A7H PRE2 PRE1 PRE0 Wdrun Wdtof Special Function Registers Table P89LPC903 F7H Psth PCH Pkbih TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# P89LPC901/902/903 Memory Organization DataSFR CodeGeneral Description Enhanced CPU Clock DefinitionsCPU Clock Oscclk Low Speed Oscillator Option P89LPC901Clock Output P89LPC901 Oscillator Option Selection- P89LPC901On-Chip RC oscillator Option BIT Symbol Function Watchdog Oscillator OptionExternal Clock Input Option P89LPC901 TrimHigh freq Med freqLow freq DivmAtchdog CPU Clock Cclk Wakeup Delay CPU Clock Cclk Modification Divm RegisterL K O sc illa to rP89LPC901/902/903 Low Power Select P89LPC901 P89LPC901/902/903 Interrupt Priority Structure Flag Bits Address Enable Bits Priority Ranking Summary of Interrupts P89LPC901 DescriptionInterrupt Arbitration Summary of Interrupts P89LPC902 DescriptionP89LPC901/902/903 External Interrupt Inputs External Interrupt Pin Glitch SuppressionTF1 ET1 TI & RI/RI ES/ESR Port Configurations Quasi-Bidirectional Output ConfigurationNumber of I/O Pins Available Clock Source Reset Option RSTOpen Drain Output Configuration Quasi-Bidirectional OutputPush-Pull Output Configuration P89LPC901/902/903 Input-Only ConfigurationPort 0 Analog Functions Additional Port Features Port Output Configuration P89LPC901Port Output Configuration P89LPC902 Port Output Configuration P89LPC903Ports Ports Tmod TMOD.7TMOD.6 TMOD.3Mode Tamod P89LPC901TAMOD.7-1 TAMOD.0Mode 6 P89LPC901 P89LPC901/902/903 ModeTcon Timer/Counter 0 or 1 in Mode 0 13-bit counter PclkPclk TL0 Timer Overflow toggle output P89LPC901TR0 ENT0 Pclk TH0 Timers 0 Real-time clock/system timer Block Diagram Real-time Clock SourceReal-time Clock/System Timer Clock Source P89LPC901 FOSC2 FOSC1 FOSC0 RTCS10UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock Frequency XclkReset Sources Affecting the Real-time Clock Real-time Clock/System Timer Clock Source P89LPC902/903Changing RTCS1-0 Real-time Clock Interrupt/Wake UpRtccon Brownout Detection Power-On Detection Brownout OptionsP89LPC901/902/903 Power Reduction Modes Power Reduction ModesPcon Pcona Power Monitoring Functions Uart P89LPC903 P89LPC901/902/903 SFR Space Baud Rate Generator and SelectionUpdating the BRGR1 and BRGR0 SFRs SFR Locations for UARTsBreak Detect Framing ErrorBrgcon Scon More About Uart Mode SstatSerial Port Mode 0 Double Buffering Must Be Disabled Framing Error and RI in Modes 2 and 3 with SM2 = FE and RI when SM2 = 1 in Modes 2P89LPC901/902/903 More About Uart Modes 2 PCON.6 RB8 SMOD0P89LPC901/902/903 Double Buffering Double Buffering in Different Modes9th Bit Bit 8 in Double Buffering Modes 1, 2 Transmission with and without Double BufferingMultiprocessor Communications Automatic Address RecognitionUart P89LPC903 Uart P89LPC903 Power-On reset code execution Block Diagram of ResetRstsrc Comparator Configuration CMPnComparator Input and Output Connections P89LPC901 Comparator Interrupt Internal Reference VoltageCmpref Comparator and Power Reduction Modes Comparator Configuration ExampleKbpatn KBPATN.5,4Kbcon KbmaskKBMASK.7 KBMASK.6KBMASK.3 KBMASK.2Keypad Interrupt KBI Watchdog Function Watchdog timer configurationWdte Wdse Function Feed Sequence Wdcon Prescaler Reset Pclk P89LPC901/902/903 Watchdog Timeout ValuesWDCONA7H P89LPC901/902/903 Watchdog Timer in Timer Mode Power down operationWatchdog Clock Source PrescalerWatchdog Timer Watchdog Timer Watchdog Timer Dual Data Pointers Software ResetAUXR1 MOVXA, @DPTR MOVCA, @A+DPTRMOVX@DPTR, a Features Using Flash as data storageGeneral description Introduction to IAP-LiteFlash Program Memory Fmcon Accessing additional flash elements C-language routine to erase/program all or part of aReading additional flash elements Erase-programming additional flash elementsUCFG1 Fmadrl User Configuration Bytes C-language routine to read a flash elementUCFG1 P89LPC901User Security Bytes SECxP89LPC901/902/903 Boot Vector Boot StatusBootvec BootstatArithmetic LogicalMnemonic Description Bytes Cycles Hex Code Data TransferBoolean BranchingReti B8-BFD8-DF MiscellaneousRevision History 108 Index Dual Data Pointers Port 0 12, 14 SFR 113 P89LPC901/902/903

P89LPC903, P89LPC902, P89LPC901 specifications

The Philips P89LPC901, P89LPC902, and P89LPC903 are a series of 8-bit microcontrollers designed for embedded system applications. These models, which belong to the LPC900 series, are notable for their affordability and versatility, making them an attractive choice for both hobbyists and professional developers.

One of the core features of the P89LPC901, P89LPC902, and P89LPC903 microcontrollers is their powerful 8-bit architecture. Operating at clock speeds up to 20 MHz, they deliver efficient performance suited for a range of tasks. Each model includes a comprehensive instruction set that supports various data manipulation and arithmetic functions, enabling extensive programming capabilities.

These microcontrollers come with built-in memory, with configurations that vary among the three models. The P89LPC901 typically features 4 KB of Flash memory and 256 bytes of RAM, while the P89LPC902 and P89LPC903 offer enhanced memory options. This Flash memory allows for reprogrammability, making it easier to update and modify applications as needed.

Another significant characteristic of the LPC900 series is their integrated peripherals. These models are equipped with a variety of I/O ports, allowing for easy interfacing with other devices and components. The P89LPC901 supports up to 32 I/O pins, while the P89LPC902 and P89LPC903 provide additional features such as analog-to-digital converters (ADCs), timers, and serial communication interfaces. This broad range of peripherals empowers developers to design complex applications without needing extra hardware.

Power consumption is also a key consideration for microcontroller applications. The P89LPC901, P89LPC902, and P89LPC903 are designed with low power consumption in mind, making them ideal for battery-operated devices and energy-efficient projects. They can operate in various power modes, allowing for greater flexibility in deployment.

In terms of technology, these microcontrollers utilize advanced CMOS technology, ensuring high reliability and durability. Their design offers a robust solution for numerous applications, including consumer electronics, industrial controls, and automation systems.

In summary, the Philips P89LPC901, P89LPC902, and P89LPC903 microcontrollers present an attractive combination of performance, integrated peripherals, low power consumption, and versatility. Their features cater to a wide array of applications, keeping them relevant in a rapidly evolving technology landscape. For hobbyists and professionals alike, these microcontrollers represent a reliable foundation for embedded system development.