Philips P89LPC902, P89LPC903 user manual P89LPC901/902/903 Mode, Mode 6 P89LPC901, Tcon

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Philips Semiconductors

User’s Manual - Preliminary -

 

 

 

 

 

 

TIMERS 0 AND 1

P89LPC901/902/903

 

 

Mode 3

 

 

When Timer 1 is in Mode 3 it is stopped. The effect is the same as setting TR1 = 0.

Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for Mode 3 on Timer 0 is shown in Figure 5-7. TL0 uses the Timer 0 control bits: TR0 and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the “Timer 1” interrupt.

Mode 3 is provided for applications that require an extra 8-bit timer.

Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still be used by the serial port as a baud rate generator (P89LPC903 only), or in any application not requiring an interrupt.

Mode 6 - P89LPC901

In this mode, Timer 0 can be changed to a PWM with a full period of 256 timer clocks (see Figure 5-8). Its structure is similar to mode 2, except that:

•TF0 is set and cleared in hardware;

•The low period of the TF0 is in TH0, and should be between 1 and 254, and;

•The high period of the TF0 is always 256-TH0.

•Loading TH0 with 00h will force the T0 pin high, loading TH0 with FFh will force the T0 pin low.

Note that an interrupt can still be enabled on the low to high transition of TF0, and that TF0 can still be cleared in software as in any other modes.

TCON

 

7

6

5

4

3

2

 

1

0

 

Address: 88h

 

 

TF1

TR1

TF0

TR0

-

-

 

-

-

 

Bit addressable

 

 

 

 

 

 

 

 

 

 

 

 

Reset Source(s): Any reset

 

 

 

 

 

 

 

 

 

 

 

Reset Value: 00000000B

 

 

 

 

 

 

 

 

 

 

 

BIT

SYMBOL

FUNCTION

 

 

 

 

 

 

 

 

 

TCON.7

TF1

Timer 1 overflow flag. Set by hardware on Timer overflow. Cleared by hardware when the

 

 

interrupt is processed, or by software.

 

 

 

 

 

 

TCON.6

TR1

Timer 1 Run control bit. Set/cleared by software to turn Timer 1 on/off.

 

 

TCON.5

TF0

Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware

 

 

when the processor vectors to the interrupt routine, or by software. (except in mode 6, see

 

 

above, when it is cleared in hardware)

 

 

 

 

 

 

TCON.4

TR0

Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.

TCON.3

-

Reserved for future use. Should not be set to 1 by user programs.

 

 

 

TCON.2

-

Reserved for future use. Should not be set to 1 by user programs.

 

 

 

TCON.1

-

Reserved for future use. Should not be set to 1 by user programs.

 

 

 

TCON.0

-

Reserved for future use. Should not be set to 1 by user programs.

 

 

 

Figure 5-3: Timer/Counter Control register (TCON)

2003 Dec 8

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Contents Philips Semiconductors User ManualTable of Contents Power Monitoring Functions 103 P89LPC901/902/903 List of Figures P89LPC902 Pin ConfigurationsProduct comparison Logic SymbolsCPU Block Diagram P89LPC901High Performance Accelerated 2-clock 80C51 CPU Block Diagram P89LPC902Uart Block Diagram P89LPC903KBI5 Mnemonic PIN no Type Name and FunctionCIN1A KBI4XTAL1 P3.1KBI2 CMP2KBI0 CIN2ARxD P1.0TxD P1.1Special Function Registers Table P89LPC901 Special Function RegistersBit Functions and Addresses Hex Special Function Registers Table P89LPC902 CMP1 Cmpref CIN1A KB2 KB0 KB6 KB5 KB4 A7H PRE2 PRE1 PRE0 Wdrun Wdtof Special Function Registers Table P89LPC903 F7H Psth PCH Pkbih TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0 WDCON# Code P89LPC901/902/903 Memory OrganizationData SFRGeneral Description Low Speed Oscillator Option P89LPC901 Enhanced CPUClock Definitions CPU Clock OscclkOn-Chip RC oscillator Option Oscillator Option Selection- P89LPC901Clock Output P89LPC901 Trim BIT Symbol FunctionWatchdog Oscillator Option External Clock Input Option P89LPC901Divm High freqMed freq Low freqAtchdog O sc illa to r CPU Clock Cclk Wakeup DelayCPU Clock Cclk Modification Divm Register L KP89LPC901/902/903 Low Power Select P89LPC901 P89LPC901/902/903 Interrupt Priority Structure Summary of Interrupts P89LPC902 Description Flag Bits Address Enable Bits Priority RankingSummary of Interrupts P89LPC901 Description Interrupt ArbitrationExternal Interrupt Pin Glitch Suppression P89LPC901/902/903 External Interrupt InputsTF1 ET1 TI & RI/RI ES/ESR RST Port ConfigurationsQuasi-Bidirectional Output Configuration Number of I/O Pins Available Clock Source Reset OptionQuasi-Bidirectional Output Open Drain Output ConfigurationPort 0 Analog Functions P89LPC901/902/903 Input-Only ConfigurationPush-Pull Output Configuration Port Output Configuration P89LPC903 Additional Port FeaturesPort Output Configuration P89LPC901 Port Output Configuration P89LPC902Ports Ports TMOD.3 TmodTMOD.7 TMOD.6TAMOD.0 ModeTamod P89LPC901 TAMOD.7-1Tcon P89LPC901/902/903 ModeMode 6 P89LPC901 Pclk Timer/Counter 0 or 1 in Mode 0 13-bit counterTR0 ENT0 Pclk TH0 Timer Overflow toggle output P89LPC901Pclk TL0 Timers 0 Real-time Clock Source Real-time clock/system timer Block DiagramXclk Real-time Clock/System Timer Clock Source P89LPC901FOSC2 FOSC1 FOSC0 RTCS10 UCFG1.2 UCFG1.1 UCFG1.0 Cclk Frequency RTC Clock FrequencyReal-time Clock Interrupt/Wake Up Reset Sources Affecting the Real-time ClockReal-time Clock/System Timer Clock Source P89LPC902/903 Changing RTCS1-0Rtccon Brownout Detection Brownout Options Power-On DetectionPower Reduction Modes P89LPC901/902/903 Power Reduction ModesPcon Pcona Power Monitoring Functions Uart P89LPC903 SFR Locations for UARTs P89LPC901/902/903 SFR SpaceBaud Rate Generator and Selection Updating the BRGR1 and BRGR0 SFRsBrgcon Framing ErrorBreak Detect Scon Sstat More About Uart ModeSerial Port Mode 0 Double Buffering Must Be Disabled PCON.6 RB8 SMOD0 Framing Error and RI in Modes 2 and 3 with SM2 =FE and RI when SM2 = 1 in Modes 2 P89LPC901/902/903 More About Uart Modes 2Double Buffering in Different Modes P89LPC901/902/903 Double BufferingTransmission with and without Double Buffering 9th Bit Bit 8 in Double Buffering Modes 1, 2Automatic Address Recognition Multiprocessor CommunicationsUart P89LPC903 Uart P89LPC903 Block Diagram of Reset Power-On reset code executionRstsrc CMPn Comparator ConfigurationComparator Input and Output Connections P89LPC901 Cmpref Internal Reference VoltageComparator Interrupt Comparator Configuration Example Comparator and Power Reduction ModesKBPATN.5,4 KbpatnKbmask KbconKBMASK.2 KBMASK.7KBMASK.6 KBMASK.3Keypad Interrupt KBI Wdte Wdse Function Watchdog timer configurationWatchdog Function Feed Sequence Wdcon WDCONA7H P89LPC901/902/903 Watchdog Timeout ValuesPrescaler Reset Pclk Prescaler P89LPC901/902/903 Watchdog Timer in Timer ModePower down operation Watchdog Clock SourceWatchdog Timer Watchdog Timer Watchdog Timer AUXR1 Software ResetDual Data Pointers MOVX@DPTR, a MOVCA, @A+DPTRMOVXA, @DPTR Introduction to IAP-Lite FeaturesUsing Flash as data storage General descriptionFlash Program Memory Fmcon C-language routine to erase/program all or part of a Accessing additional flash elementsUCFG1 Erase-programming additional flash elementsReading additional flash elements Fmadrl C-language routine to read a flash element User Configuration BytesP89LPC901 UCFG1SECx User Security BytesBootstat P89LPC901/902/903 Boot VectorBoot Status BootvecLogical ArithmeticData Transfer Mnemonic Description Bytes Cycles Hex CodeBranching BooleanMiscellaneous RetiB8-BF D8-DFRevision History 108 Index Dual Data Pointers Port 0 12, 14 SFR 113 P89LPC901/902/903

P89LPC903, P89LPC902, P89LPC901 specifications

The Philips P89LPC901, P89LPC902, and P89LPC903 are a series of 8-bit microcontrollers designed for embedded system applications. These models, which belong to the LPC900 series, are notable for their affordability and versatility, making them an attractive choice for both hobbyists and professional developers.

One of the core features of the P89LPC901, P89LPC902, and P89LPC903 microcontrollers is their powerful 8-bit architecture. Operating at clock speeds up to 20 MHz, they deliver efficient performance suited for a range of tasks. Each model includes a comprehensive instruction set that supports various data manipulation and arithmetic functions, enabling extensive programming capabilities.

These microcontrollers come with built-in memory, with configurations that vary among the three models. The P89LPC901 typically features 4 KB of Flash memory and 256 bytes of RAM, while the P89LPC902 and P89LPC903 offer enhanced memory options. This Flash memory allows for reprogrammability, making it easier to update and modify applications as needed.

Another significant characteristic of the LPC900 series is their integrated peripherals. These models are equipped with a variety of I/O ports, allowing for easy interfacing with other devices and components. The P89LPC901 supports up to 32 I/O pins, while the P89LPC902 and P89LPC903 provide additional features such as analog-to-digital converters (ADCs), timers, and serial communication interfaces. This broad range of peripherals empowers developers to design complex applications without needing extra hardware.

Power consumption is also a key consideration for microcontroller applications. The P89LPC901, P89LPC902, and P89LPC903 are designed with low power consumption in mind, making them ideal for battery-operated devices and energy-efficient projects. They can operate in various power modes, allowing for greater flexibility in deployment.

In terms of technology, these microcontrollers utilize advanced CMOS technology, ensuring high reliability and durability. Their design offers a robust solution for numerous applications, including consumer electronics, industrial controls, and automation systems.

In summary, the Philips P89LPC901, P89LPC902, and P89LPC903 microcontrollers present an attractive combination of performance, integrated peripherals, low power consumption, and versatility. Their features cater to a wide array of applications, keeping them relevant in a rapidly evolving technology landscape. For hobbyists and professionals alike, these microcontrollers represent a reliable foundation for embedded system development.
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