Quatech QSC-100 user manual General Information

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1 General Information

The Quatech, Inc. QSC-100 provides four RS-232 asynchronous serial communication interfaces for IBM-compatible personal computer systems using the PCI expansion bus. The QSC-100 uses Quatech's new Enhanced Serial Adapter design. Legacy serial port data rates are limited to a maximum of 115,200 bits per second. Quatech Enhanced Serial Adapters can achieve data rates as high as 921,600 bits per second.

As a PCI device, the QSC-100 requires no hardware configuration. The card is automatically configured by the computer's BIOS or operating system. The four serial ports share a single interrupt line and are addressed in a contiguous block of 32 bytes. A special interrupt status register is provided to help software to manage the shared interrupt.

The QSC-100's serial ports are using 16750 Universal Asynchronous Receiver/Transmitters (UARTs). These UARTs contain hardware buffers (FIFOs) which reduce processing overhead and allow higher data rates to be achieved. The 16750 contains a 64-byte FIFO and can transmit and receive data at a rate of up to 921,600 bits per second and is recommended for heavy multitasking environments and for applications involving high data rates. The larger FIFO allows each read or write access to the UART to move more data, resulting in fewer interrupts and less processor time spent servicing the UART.

The QSC-100 is supported under several popular operating systems and environments. Contact the sales department for details on current software offerings. Most device drivers are available for download from the Quatech world wide web site at http://www.quatech.com.

Quatech serial device drivers for Windows 95, Windows NT, 98, 2000, Millennium and OS/2 provide support for the UART's 16750 mode.

Quatech QSC-100 User's Manual

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Contents QSC-100 Warranty Information Declaration of Conformity Type of Equipment Application of Council DirectiveStandards to which Conformity is Declared Equipment ClassQTPCI.EXE General Information Features IND Option --- Surge Suppression UpgradePart Number IND Option Hardware Configuration Factory Default ConfigurationEnable Scratchpad Register SPAD, J6 Force High-Speed Uart Clock X2, X4, or X8, J3-J5 Clock multiplier jumper optionsHardware Installation Jumper/connector locationsAddress Map and Special Registers Base Address and Interrupt Level IRQPort Address Range Dlab Bit Spad Jumper Register selected for Enabling the Special RegistersInterrupt Status Register Bit DescriptionClock Rate Multiplier Options RegisterEnhanced Serial Adapter Identification Bit Name DescriptionRR1 RR0 Clock Rate Uart Clock Maximum Data Multiplier FrequencyWindows Configuration Windows MillenniumWindows Page Windows Viewing Resources with Device Manager Windows NT Page DOS and Other Operating Systems QTPCI.EXEQTPCI.EXE Basic Mode display QTPCI.EXE Expert Mode display OS/2 External Connections RS-232 Port Signal QSC-100 connector pinoutsPCI Resource Map INTA#Specifications Page Troubleshooting Computer will not boot upCannot communicate with other equipment QSC-100 Revision March
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