Quatech QSC-100 Enabling the Special Registers, Interrupt Status Register, Bit Description

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4.2 Enabling the Special Registers

The QSC-100 contains two unique registers, an Interrupt Status Register and an Options Register. These registers are enabled when the SPAD jumper (J6) is removed (factory default). They replace the UART Scratchpad Register on accesses to register address 7.

The Interrupt Status Register and Options Register are accessed through the scratchpad location of any UART. The DLAB bit of the UART (Line Control Register, bit 7) is used to select between the two registers. The most recent write of a DLAB bit in any UART selects between the two registers as shown in Figure 6.

DLAB Bit

SPAD Jumper

Register selected for

address 7 accesses

 

 

0

removed

Interrupt Status Register

1

removed

Options Register

X

applied

Scratchpad Registers

Figure 7 --- DLAB bit selects between special registers

4.3 Interrupt Status Register

The read-only Interrupt Status Register can be used to quickly identify which serial ports require servicing after an interrupt. Reading the Interrupt Status Register will return the interrupt status of the entire QSC-100, as shown in Figure 7. The individual bits are cleared as the interrupting ports are serviced. The interrupt service routine should ensure that the interrupt status register reads zero before exiting.

Bit

Description

 

 

7 (MSB)

0 (not used)

6

0 (not used)

 

 

5

0 (not used)

 

 

4

0 (not used)

3

Port 4 --- 1 if interrupt pending

 

 

2

Port 3 --- 1 if interrupt pending

 

 

1

Port 2 --- 1 if interrupt pending

 

 

0

Port 1 --- 1 if interrupt pending

 

 

Figure 8 --- Interrupt Status Register

Quatech QSC-100 User's Manual

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Contents QSC-100 Warranty Information Declaration of Conformity Application of Council Directive Standards to which Conformity is DeclaredType of Equipment Equipment ClassQTPCI.EXE General Information Features IND Option --- Surge Suppression UpgradePart Number IND Option Hardware Configuration Factory Default ConfigurationEnable Scratchpad Register SPAD, J6 Force High-Speed Uart Clock X2, X4, or X8, J3-J5 Clock multiplier jumper optionsHardware Installation Jumper/connector locationsAddress Map and Special Registers Base Address and Interrupt Level IRQPort Address Range Enabling the Special Registers Interrupt Status RegisterDlab Bit Spad Jumper Register selected for Bit DescriptionOptions Register Enhanced Serial Adapter IdentificationClock Rate Multiplier Bit Name DescriptionRR1 RR0 Clock Rate Uart Clock Maximum Data Multiplier FrequencyWindows Configuration Windows MillenniumWindows Page Windows Viewing Resources with Device Manager Windows NT Page DOS and Other Operating Systems QTPCI.EXEQTPCI.EXE Basic Mode display QTPCI.EXE Expert Mode display OS/2 External Connections RS-232 Port Signal QSC-100 connector pinoutsPCI Resource Map INTA#Specifications Page Troubleshooting Computer will not boot upCannot communicate with other equipment QSC-100 Revision March
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