Cypress CY14B108K manuals
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29 pages 851.81 Kb
PRELIMINARY CY14B108K, CY14B108M 8 Mbit (1024K x 8/512K x 16) nvSRAM with Real Time Clock,Cypress Semiconductor Corporation 198 Champion Court San Jose CA 95134-1709 408-943-2600 Document #: 001-47378 Rev. ** Revised April 01, 2009 Features Logic Block DiagramSTORE to QuantumTrap 20 ns, 25 ns, and 45 ns access times Internally organized as 1024K x 8 (CY14B108K) or 512K x 16 (CY14B108M) Hands off automatic STORE on power down with only a small capacitor nonvolatile elements is initiated by software, device pin, or AutoStore on power down RECALL to SRAM initiated by software or power up High reliability Infinite Read, Write, and RECALL cycles 200,000 STORE cycles to QuantumTrap 20 year data retention Single 3V +20%, 10% operation Data integrity of Cypress nvSRAM combined with full featured Real Time Clock (RTC) Watchdog timer Clock alarm with programmable interrupts Capacitor or battery backup for RTC Commercial and industrial temperatures 44 and 54-pin TSOP II package Pb-free and RoHS compliance Functional Description[1, 2, 3]Notes 1. Address A - A for x8 configuration and Address A - A for x16 configuration. 2. Data DQ - DQ for x8 configuration and Data DQ - DQ for x16 configuration. 3. BHE and BLE are applicable for x16 configuration only. Document #: 001-47378 Rev. ** Page 2 of 29 2 Pinouts is used. Figure 1. Pin Diagram: 44-PIn and 54-Pin TSOP II Table 1. Pin Definitions Pin Name I/O Type Description A A Input Address Inputs Used to Select one of the 1,048,576 bytes of the nvSRAM for x8 Configuration. A A Address Inputs Used to Select one of the 524,288 words of the nvSRAM for x16 Configuration. DQ DQ DQ0 DQ15 - DQ . BLE Input Byte Low Enable, Active LOW. Controls DQ - DQ . X Output Crystal Connection. Drives crystal on start up. X Input Crystal Connection. For 32.768 KHz crystal. V Power Supply Capacitor Supplied Backup RTC Supply Voltage. Left unconnected if V is used. V Power Supply Battery Supplied Backup RTC Supply Voltage. Left unconnected if V44 - TSOP II Top View (not to scale)54 - TSOP II Top View (not to scale) 3 Device OperationSRAM Read SRAM Write AutoStore Operation 4 PRELIMINARY CY14B108K, CY14B108M8 PRELIMINARY CY14B108K, CY14B108MCalibrating the Clock Alarm Watchdog Timer 9 Power MonitorInterrupts Interrupt Register Flags Register 10 PRELIMINARY CY14B108K, CY14B108MFigure 4. RTC Recommended Component Configuration Figure 5. Interrupt Block Diagram 14 PRELIMINARY CY14B108K, CY14B108M15 Maximum RatingsOperating Range DC Electrical Characteristics 16 AC Test ConditionsData Retention and Endurance Capacitance Thermal Resistance 18 AC Switching Characteristics 21 AutoStore/Power Up RECALL22 Software Controlled STORE and RECALL CycleIn the following table, the software controlled STORE and RECALL cycle parameters are listed. Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max STORE/RECALL Initiation Cycle Time 20 25 45 ns Address Setup Time 0 0 0 ns Clock Pulse Width 152030 ns Address Hold Time 0 0 0 ns RECALL Duration 200 200 200 s Soft Sequence Processing Time 100 100 100 s Figure 13. CE and OE Controlled Software STORE and RECALL Cycle Figure 14. AutoStore Enable and Disable Cycle Hardware STORE CycleParameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max Figure 15. Hardware STORE Cycle HSB To Output Active Time when write latch not set 20 25 25 ns Hardware STORE Pulse Width 15 15 15 ns Figure 16. Soft Sequence Processing 23 Write latch setWrite latch not set
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