Data Output High Impedance Output Data Valid

PRELIMINARY	CY14B108K, CY14B108M

Switching Waveforms

Figure 8. SRAM Read Cycle 2: CE Controlled[3, 15, 19]

Address

Address Valid

		tRC	tHZCE
CE		tACE
CE
		tAA
		tLZCE	t
			HZOE
OE		tDOE
OE
		tLZOE	tHZBE
BHE, BLE		tDBE
BHE, BLE
		tLZBE
Data Output	High Impedance		Output Data Valid
Data Output		tPU	Output Data Valid
		tPU	tPD
			tPD
ICC	Standby	Active
	Figure 9. SRAM Write Cycle 1: WE Controlled[3, 18, 19, 20]
		tWC
Address		Address Valid
		tSCE	tHA
CE
		tBW
BHE, BLE
		tAW
		tPWE
WE		tSA
		tSA
		tSD	tHD
Data Input			Input Data Valid
		tHZWE	tLZWE
Data Output	Previous Data	High Impedance
Data Output	Previous Data

Note

20. CE or WE must be >VIH during address transitions.

Document #: 001-47378 Rev. **

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Cypress CY14B108M, CY14B108K manual Data Output High Impedance Output Data Valid, Standby Active, Address Address Valid

Contents

Cypress Semiconductor Corporation FeaturesLogic Block Diagram1, 2 Functional Description Pinouts AutoStore Operation Device OperationSram Read Sram Write Software Store Hardware Recall Power UpHardware Store HSB Operation Software Recall Store Mode SelectionA15 A05 Mode Power Preventing AutoStore Noise Considerations Data Protection Best Practices Real Time Clock Operation Watchdog Timer AlarmCalibrating the Clock Flags Register Power MonitorInterrupt Register Interrupts AF Alarm Flag WDF Watchdog Timer FlagPF Power Fail Flag PFE Power Fail Enable WDS OscenWDF Oscf For the register is 0 to 0xFFFF9 0x7FFF9 Time Keeping Seconds 0xFFFF6 0x7FFF6 Interrupt Status/Control 0xFFFF5 0x7FFF5 Alarm DayTime-base Write only. Reading it always returns a This condition and write 0 to clear this flag 0xFFFF2 0x7FFF2 Alarm SecondsCenturies 0xFFFF0 0x7FFF0 Flags Watchdog Operating Range DC Electrical CharacteristicsRange Ambient Temperature Maximum Ratings AC Test Conditions Data Retention and EnduranceCapacitance Thermal Resistance RTC Capacitor Pin Voltage TOCS RTC Oscillator Time to Start RTC Backup CurrentHot Temperature 85 oC RTC Battery Pin Voltage Sram Write Cycle AC Switching CharacteristicsSwitching Waveforms Parameters Sram Read Cycle Data Input Input Data Valid Data Output High Impedance Output Data ValidStandby Active Address Address Valid Data Input Input Data Valid High Impedance Data Output Data Input Data OutputInput Data Valid High Impedance Not applicable for RTC register writes Parameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up Recall Software Controlled Store and Recall Cycle Hardware Store Pulse Width To Output Active Time when write latch not setHardware Store Cycle Description 20 ns 25 ns 45 ns Unit Min Truth Table For Sram Operations For x8 ConfigurationFor x16 Configuration Inputs and Outputs Mode Power ZS Tsop Part Numbering Nomenclature CY14 B 108 K ZS P 20 X C TNvsram Ordering Information Pin Tsop II Package Diagrams 51-85160 Document History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions New Data Sheet

Switching Waveforms

Figure 8. SRAM Read Cycle 2: CE Controlled[3, 15, 19]

BHE, BLE

Data Output

High Impedance

Output Data Valid

Standby

Active

Figure 9. SRAM Write Cycle 1: WE Controlled[3, 18, 19, 20]

Address

Address Valid

Data Input

Input Data Valid

Data Output

Previous Data

High Impedance