Data Input Data Output | Cypress CY14B108K, CY14B108M manual

PRELIMINARY	CY14B108K, CY14B108M

Switching Waveforms

Figure 10. SRAM Write Cycle 2: CE Controlled[3, 18, 19, 20]

Address

BHE, BLE

Data Input

Data Output

	tWC
	Address Valid
tSA	tSCE	tHA
	tBW
	tPWE
	tSD	tHD
	Input Data Valid
	High Impedance

Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled[5, 18, 19, 20, 21]
(Not applicable for RTC register writes)
	tWC
Address	Address Valid
	tSCE
CE
tSA	tBW	tHA
BHE, BLE
	tAW
	tPWE
WE
	tSD	tHD
Data Input	Input Data Valid
	High Impedance
Data Output

Note

21. Only CE and WE controlled writes to RTC registers are allowed. BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register.

Document #: 001-47378 Rev. **

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Cypress CY14B108K manual Data Input Data Output, Input Data Valid High Impedance, Not applicable for RTC register writes

Contents

Features Logic Block Diagram1, 2Functional Description Cypress Semiconductor Corporation Pinouts Device Operation Sram ReadSram Write AutoStore Operation Hardware Recall Power Up Hardware Store HSB OperationSoftware Recall Software Store Mode Selection A15 A05 Mode PowerPreventing AutoStore Store Data Protection Best Practices Noise Considerations Real Time Clock Operation Calibrating the Clock AlarmWatchdog Timer Power Monitor Interrupt RegisterInterrupts Flags Register WDF Watchdog Timer Flag PF Power Fail FlagPFE Power Fail Enable AF Alarm Flag WDF Oscf OscenWDS 0xFFFF9 0x7FFF9 Time Keeping Seconds For the register is 0 to 0xFFFF5 0x7FFF5 Alarm Day Time-baseWrite only. Reading it always returns a 0xFFFF6 0x7FFF6 Interrupt Status/Control 0xFFFF2 0x7FFF2 Alarm Seconds Centuries 0xFFFF0 0x7FFF0 FlagsWatchdog This condition and write 0 to clear this flag DC Electrical Characteristics Range Ambient TemperatureMaximum Ratings Operating Range Data Retention and Endurance CapacitanceThermal Resistance AC Test Conditions RTC Backup Current Hot Temperature 85 oCRTC Battery Pin Voltage RTC Capacitor Pin Voltage TOCS RTC Oscillator Time to Start AC Switching Characteristics Switching WaveformsParameters Sram Read Cycle Sram Write Cycle Data Output High Impedance Output Data Valid Standby ActiveAddress Address Valid Data Input Input Data Valid Data Input Data Output Input Data Valid High ImpedanceNot applicable for RTC register writes Data Input Input Data Valid High Impedance Data Output AutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min Max Software Controlled Store and Recall Cycle To Output Active Time when write latch not set Hardware Store CycleDescription 20 ns 25 ns 45 ns Unit Min Hardware Store Pulse Width For x8 Configuration For x16 ConfigurationInputs and Outputs Mode Power Truth Table For Sram Operations Nvsram Part Numbering Nomenclature CY14 B 108 K ZS P 20 X C TZS Tsop Ordering Information Package Diagrams Pin Tsop II 51-85160 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsNew Data Sheet Document History

Cypress CY14B108K, CY14B108M manual Data Input Data Output, Input Data Valid High Impedance

Models: CY14B108K CY14B108M

Switching Waveforms

Figure 10. SRAM Write Cycle 2: CE Controlled[3, 18, 19, 20]

BHE, BLE

Data Input

Data Output

Input Data Valid

High Impedance

Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled[5, 18, 19, 20, 21]

(Not applicable for RTC register writes)

Address

BHE, BLE

Data Input

Input Data Valid

High Impedance

Data Output