Cypress CY14B108K, CY14B108M AutoStore/Power Up RECALL

PRELIMINARY CY14B108K, CY14B108M

Document #: 001-47378 Rev. ** Page 21 of 29

AutoStore/Power Up RECALL

Parameters Description 20 ns 25 ns 45 ns Unit

Min Max Min Max Min Max

t

HRECALL [22]

Power Up RECALL Duration 20 20 20 ms

t

STORE [23]

STORE Cycle Duration 8 8 8 ms

t

DELAY [24]

Time Allowed to Complete SRAM Cycle 20 25 25 ns

V

SWITCH

Low Voltage Trigger Level 2.65 2.65 2.65 V

t

VCCRISE

VCC Rise Time 150 150 150 μs

V

HDIS[13]

HSB Output Driver Disable Voltage 1.9 1.9 1.9 V

t

LZHSB

HSB To Output Active Time 5 5 5 μs

t

HHHD

HSB High Active Time 500 500 500 ns

Switching Waveforms

Figure 12. AutoStore or Power Up RECALL

[25]

VSWITCH

VHDIS

VVCCRISE tSTORE tSTORE

tHHHD tHHHD

tDELAY

tDELAY

tLZHSB tLZHSB

tHRECALL

tHRECALL

HSBOUT

Autostore

POWER-

UP

RECALL

Read& Write

Inhibited

(RWI)

POWER-UP

RECALL

Read& W rite BROWN

OUT

Autostore

POWER-UP

RECALL

Read& Wri te POWER

DOWN

Autostore

Note23 Note23

Note26

Notes

22.t

HRECALL

starts from the time V

CC

rises above V

SWITCH.

23.If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.

24.On a Hardware STORE, Software STORE / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t

DELAY

.

25.Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V

SWITCH.

26.HSB pin is driven HIGH to VCC only by internal 100 k

Ω

resistor, HSB driver is disabled.

[+] Feedback

Contents

Main PRELIMINARY CY14B108K, CY14B108M 8 Mbit (1024K x 8/512K x 16) nvSRAM with Real Time Clock , Cypress Semiconductor Corporation 198 Champion Court San Jose CA 95134-1709 408-943-2600 Document #: 001-47378 Rev. ** Revised April 01, 2009 Features Pinouts is used. Figure 1. Pin Diagram: 44-PIn and 54-Pin TSOP II Table 1. Pin Definitions Pin Name I/O Type Description A A Device Operation SRAM Read SRAM Write AutoStore Operation PRELIMINARY CY14B108K, CY14B108M Hardware STORE (HSB) Operation Hardware RECALL (Power Up) Software STORE Software RECALL Preventing AutoStore Data Protection Noise Considerations Best Practices Real Time Clock Operation nvTime Operation Clock Operations Reading the Clock Setting the Clock PRELIMINARY CY14B108K, CY14B108M Calibrating the Clock Alarm Watchdog Timer Power Monitor Interrupts Interrupt Register Flags Register PRELIMINARY CY14B108K, CY14B108M Figure 4. RTC Recommended Component Configuration Figure 5. Interrupt Block Diagram Xout Xin V Page Page Page PRELIMINARY CY14B108K, CY14B108M Maximum Ratings Operating Range DC Electrical Characteristics AC Test Conditions Data Retention and Endurance Capacitance Thermal Resistance Page AC Switching Characteristics Figure 8. SRAM Read Cycle 2: CE Controlled Figure 9. SRAM Write Cycle 1: WE Controlled Figure 10. SRAM Write Cycle 2: CE Controlled Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled (Not applicable for RTC register writes) AutoStore/Power Up RECALL Software Controlled STORE and RECALL Cycle In the following table, the software controlled STORE and RECALL cycle parameters are listed. Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max STORE/RECALL Initiation Cycle Time 20 25 45 ns Address Setup Time 0 0 0 ns Hardware STORE Cycle Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max Figure 15. Hardware STORE Cycle HSB To Output Active Time when write latch not set 20 25 25 ns Hardware STORE Pulse Width 15 15 15 ns Truth Table For SRAM Operations For x8 Configuration For x16 Configuration Part Numbering Nomenclature CY14 B 108 K ZS P 20 X C T Ordering Information Package Diagrams Figure 17. 44-Pin TSOP II (51-85087) TOPVIEW BOTTOMVIEW 51-85087 *A Page Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions