Cypress CY14B108K, CY14B108M Ordering Information

PRELIMINARY CY14B108K, CY14B108M

Document #: 001-47378 Rev. ** Page 26 of 29

Ordering Information

Speed

(ns) Ordering Code Package

Diagram Package Type Operating

Range

20 CY14B108K-ZS20XCT 51-85087 44-pin TSOPII Commercial

CY14B108K-ZS20XC 51-85087 44-pin TSOPII

CY14B108K-ZS20XIT 51-85087 44-pin TSOPII Industrial

CY14B108K-ZS20XI 51-85087 44-pin TSOPII

CY14B108M-ZSP20XCT 51-85160 54-pin TSOPII Commercial

CY14B108M-ZSP20XC 51-85160 54-pin TSOPII

CY14B108M-ZSP20XIT 51-85160 54-pin TSOPII Industrial

CY14B108M-ZSP20XI 51-85160 54-pin TSOPII

25 CY14B108K-ZS25XCT 51-85087 44-pin TSOPII Commercial

CY14B108K-ZS25XC 51-85087 44-pin TSOPII

CY14B108K-ZS25XIT 51-85087 44-pin TSOPII Industrial

CY14B108K-ZS25XI 51-85187 44-pin TSOPII

CY14B108M-ZSP25XCT 51-85160 54-pin TSOPII Commercial

CY14B108M-ZSP25XC 51-85160 54-pin TSOPII

CY14B108M-ZSP25XIT 51-85160 54-pin TSOPII Industrial

CY14B108M-ZSP25XI 51-85160 54-pin TSOPII

45 CY14B108K-ZS45XCT 51-85087 44-pin TSOPII Commercial

CY14B108K-ZS45XC 51-85087 44-pin TSOPII

CY14B108K-ZS45XIT 51-85087 44-pin TSOPII Industrial

CY14B108K-ZS45XI 51-85187 44-pin TSOPII

CY14B108M-ZSP45XCT 51-85160 54-pin TSOPII Commercial

CY14B108M-ZSP45XC 51-85160 54-pin TSOPII

CY14B108M-ZSP45XIT 51-85160 54-pin TSOPII Industrial

CY14B108M-ZSP45XI 51-85160 54-pin TSOPII

All parts are Pb-free. The above table contains Preliminary information. Contact your local Cypress sales representative for availability of these parts.

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Contents

Main PRELIMINARY CY14B108K, CY14B108M 8 Mbit (1024K x 8/512K x 16) nvSRAM with Real Time Clock , Cypress Semiconductor Corporation 198 Champion Court San Jose CA 95134-1709 408-943-2600 Document #: 001-47378 Rev. ** Revised April 01, 2009 Features Pinouts is used. Figure 1. Pin Diagram: 44-PIn and 54-Pin TSOP II Table 1. Pin Definitions Pin Name I/O Type Description A A Device Operation SRAM Read SRAM Write AutoStore Operation PRELIMINARY CY14B108K, CY14B108M Hardware STORE (HSB) Operation Hardware RECALL (Power Up) Software STORE Software RECALL Preventing AutoStore Data Protection Noise Considerations Best Practices Real Time Clock Operation nvTime Operation Clock Operations Reading the Clock Setting the Clock PRELIMINARY CY14B108K, CY14B108M Calibrating the Clock Alarm Watchdog Timer Power Monitor Interrupts Interrupt Register Flags Register PRELIMINARY CY14B108K, CY14B108M Figure 4. RTC Recommended Component Configuration Figure 5. Interrupt Block Diagram Xout Xin V Page Page Page PRELIMINARY CY14B108K, CY14B108M Maximum Ratings Operating Range DC Electrical Characteristics AC Test Conditions Data Retention and Endurance Capacitance Thermal Resistance Page AC Switching Characteristics Figure 8. SRAM Read Cycle 2: CE Controlled Figure 9. SRAM Write Cycle 1: WE Controlled Figure 10. SRAM Write Cycle 2: CE Controlled Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled (Not applicable for RTC register writes) AutoStore/Power Up RECALL Software Controlled STORE and RECALL Cycle In the following table, the software controlled STORE and RECALL cycle parameters are listed. Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max STORE/RECALL Initiation Cycle Time 20 25 45 ns Address Setup Time 0 0 0 ns Hardware STORE Cycle Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max Figure 15. Hardware STORE Cycle HSB To Output Active Time when write latch not set 20 25 25 ns Hardware STORE Pulse Width 15 15 15 ns Truth Table For SRAM Operations For x8 Configuration For x16 Configuration Part Numbering Nomenclature CY14 B 108 K ZS P 20 X C T Ordering Information Package Diagrams Figure 17. 44-Pin TSOP II (51-85087) TOPVIEW BOTTOMVIEW 51-85087 *A Page Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions