Cypress CY14B108K, CY14B108M Write latch set, Write latch not set

PRELIMINARY CY14B108K, CY14B108M

Document #: 001-47378 Rev. ** Page 23 of 29

Hardware STORE Cycle

Parameters Description 20 ns 25 ns 45 ns Unit

Min Max Min Max Min Max

t

DHSB

HSB To Output Active Time when write latch not set 20 25 25 ns

t

PHSB

Hardware STORE Pulse Width 15 15 15 ns

Switching Waveforms

Figure 15. Hardware STORE Cycle

[23]

Figure 16. Soft Sequence Processing

[31, 32]

tPHSB

tPHSB

tDELAY tDHSB

tDELAY

tSTORE

tHHHD

tLZHSB

Write latch setWrite latch not set

HSB (IN)

HSB (OUT)

DQ(Data Out)

RWI

HSB (IN)

HSB (OUT)

RWI

HSBpin is driven high toVCC only b y Internal

SRAMis disabled as long as HSB (IN)is driven low

.

HSBd river is disabled

tDHSB

100kOhmresistor,

Address #1 Address #6 Address #1 Address #6

Soft Sequence

Command

tSS tSS

CE

Address

VCC

tSA tCW

Soft Sequence

Command

tCW

Notes

31.This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

32.Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.

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Contents

Main PRELIMINARY CY14B108K, CY14B108M 8 Mbit (1024K x 8/512K x 16) nvSRAM with Real Time Clock , Cypress Semiconductor Corporation 198 Champion Court San Jose CA 95134-1709 408-943-2600 Document #: 001-47378 Rev. ** Revised April 01, 2009 Features Pinouts is used. Figure 1. Pin Diagram: 44-PIn and 54-Pin TSOP II Table 1. Pin Definitions Pin Name I/O Type Description A A Device Operation SRAM Read SRAM Write AutoStore Operation PRELIMINARY CY14B108K, CY14B108M Hardware STORE (HSB) Operation Hardware RECALL (Power Up) Software STORE Software RECALL Preventing AutoStore Data Protection Noise Considerations Best Practices Real Time Clock Operation nvTime Operation Clock Operations Reading the Clock Setting the Clock PRELIMINARY CY14B108K, CY14B108M Calibrating the Clock Alarm Watchdog Timer Power Monitor Interrupts Interrupt Register Flags Register PRELIMINARY CY14B108K, CY14B108M Figure 4. RTC Recommended Component Configuration Figure 5. Interrupt Block Diagram Xout Xin V Page Page Page PRELIMINARY CY14B108K, CY14B108M Maximum Ratings Operating Range DC Electrical Characteristics AC Test Conditions Data Retention and Endurance Capacitance Thermal Resistance Page AC Switching Characteristics Figure 8. SRAM Read Cycle 2: CE Controlled Figure 9. SRAM Write Cycle 1: WE Controlled Figure 10. SRAM Write Cycle 2: CE Controlled Figure 11. SRAM Write Cycle 3: BHE and BLE Controlled (Not applicable for RTC register writes) AutoStore/Power Up RECALL Software Controlled STORE and RECALL Cycle In the following table, the software controlled STORE and RECALL cycle parameters are listed. Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max STORE/RECALL Initiation Cycle Time 20 25 45 ns Address Setup Time 0 0 0 ns Hardware STORE Cycle Parameters Description 20 ns 25 ns 45 ns Unit Min Max Min Max Min Max Figure 15. Hardware STORE Cycle HSB To Output Active Time when write latch not set 20 25 25 ns Hardware STORE Pulse Width 15 15 15 ns Truth Table For SRAM Operations For x8 Configuration For x16 Configuration Part Numbering Nomenclature CY14 B 108 K ZS P 20 X C T Ordering Information Package Diagrams Figure 17. 44-Pin TSOP II (51-85087) TOPVIEW BOTTOMVIEW 51-85087 *A Page Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions