Hardware Store Cycle | Cypress CY14B108M, CY14B108K specs

PRELIMINARY

CY14B108K, CY14B108M

Hardware STORE Cycle

Parameters

Description

20 ns

25 ns

45 ns

Unit

Min

Max

Min

Max

Min

Max

tDHSB

To Output Active Time when write latch not set

20

25

25

ns

HSB

tPHSB

Hardware STORE Pulse Width

15

15

15

ns

Switching Waveforms

Figure 15. Hardware STORE Cycle[23]

Write latch set

HSB (IN)

HSB (OUT)

DQ (Data Out)

RWI

tPHSB

tDELAY

tSTORE

tHHHD

tLZHSB

Write latch not set

tPHSB

HSB (IN)

HSB (OUT)

tDELAY

RWI

HSB pin is driven high to VCC only by Internal 100kOhm resistor,

HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven low.

tDHSB

tDHSB

Figure 16. Soft Sequence Processing[31, 32]

	Soft Sequence		tSS	Soft Sequence		tSS
	Command			Command
Address	Address #1	Address #6		Address #1	Address #6
	tSA		tCW		tCW
CE
VCC

Notes

31.This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

32.Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.

Document #: 001-47378 Rev. **

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Cypress CY14B108M, CY14B108K manual Hardware Store Cycle, Description 20 ns 25 ns 45 ns Unit Min, Hardware Store Pulse Width

Contents

Cypress Semiconductor Corporation FeaturesLogic Block Diagram1, 2 Functional Description Pinouts AutoStore Operation Device OperationSram Read Sram Write Software Store Hardware Recall Power UpHardware Store HSB Operation Software Recall Store Mode SelectionA15 A05 Mode Power Preventing AutoStore Noise Considerations Data Protection Best Practices Real Time Clock Operation Calibrating the Clock AlarmWatchdog Timer Flags Register Power MonitorInterrupt Register Interrupts AF Alarm Flag WDF Watchdog Timer FlagPF Power Fail Flag PFE Power Fail Enable WDF Oscf OscenWDS For the register is 0 to 0xFFFF9 0x7FFF9 Time Keeping Seconds 0xFFFF6 0x7FFF6 Interrupt Status/Control 0xFFFF5 0x7FFF5 Alarm DayTime-base Write only. Reading it always returns a This condition and write 0 to clear this flag 0xFFFF2 0x7FFF2 Alarm SecondsCenturies 0xFFFF0 0x7FFF0 Flags Watchdog Operating Range DC Electrical CharacteristicsRange Ambient Temperature Maximum Ratings AC Test Conditions Data Retention and EnduranceCapacitance Thermal Resistance RTC Capacitor Pin Voltage TOCS RTC Oscillator Time to Start RTC Backup CurrentHot Temperature 85 oC RTC Battery Pin Voltage Sram Write Cycle AC Switching CharacteristicsSwitching Waveforms Parameters Sram Read Cycle Data Input Input Data Valid Data Output High Impedance Output Data ValidStandby Active Address Address Valid Data Input Input Data Valid High Impedance Data Output Data Input Data OutputInput Data Valid High Impedance Not applicable for RTC register writes Parameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up Recall Software Controlled Store and Recall Cycle Hardware Store Pulse Width To Output Active Time when write latch not setHardware Store Cycle Description 20 ns 25 ns 45 ns Unit Min Truth Table For Sram Operations For x8 ConfigurationFor x16 Configuration Inputs and Outputs Mode Power Nvsram Part Numbering Nomenclature CY14 B 108 K ZS P 20 X C TZS Tsop Ordering Information Pin Tsop II Package Diagrams 51-85160 Document History Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions New Data Sheet