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Freescale Semiconductor 56F8322 Manual
137 pages 873.73 Kb
2 Document Revision HistoryPlease see http://www.freescale.com for the most current Data Sheet revision. 56F8322/56F8122 Block Diagram56F8322 Technical Data, Rev. 10.0 Freescale Semiconductor 3 IPBus Bridge (IPBB)Decoding PeripheralsSystem Bus Control PWMA or SPI1 or GPIOA 3 56F8322/56F8122 General DescriptionNote: Features in italics are NOT available in the 56F8122 device. 4 Table of ContentsPart 1: Overview . . . . . . . . . . . . . . . . . . . . . . 5 Part 2: Signal/Connection Descriptions . . 14 Part 13: Ordering Information . . . . . . . . . 135 Part 3: On-Chip Clock Synthesis (OCCS) . 26 Part 4: Memory Map . . . . . . . . . . . . . . . . . . 3 0 Part 5: Interrupt Controller (ITCN) . . . . . . . 52 Part 6: System Integration Module (SIM) . . 77 Part 7: Security Features . . . . . . . . . . . . . . 93 Part 8: General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . 96 Part 9: Joint Test Action Group (JTAG) . . . 98 Part 10: Specifications . . . . . . . . . . . . . . . . 99 Part 11: Packaging . . . . . . . . . . . . . . . . . . 127 Part 12: Design Considerations . . . . . . . . 132 5 Part 1 Overview14 Part 2 Signal/Connection Descriptions2.1 IntroductionTable2-1 Functional Group Pin Allocations 15 56F8322Figure 2-1 56F8322 Signals Identified by Functional Group (48-Pin LQFP)Note: VREFH is tied to VDDA and VREFLO is tied to VSSA inside this package 56F8322 Technical Data, Rev. 10.0 Freescale Semiconductor 15 16 56F8122Figure 2-2 56F8122 Signals Identified by Functional Group (48-Pin LQFP)56F8322 Techncial Data, Rev. 10.0 16 Freescale Semiconductor 17 2.2 Signal Pins26 Part 3 On-Chip Clock Synthesis (OCCS)30 Part 4 Memory Map52 Part 5 Interrupt Controller (ITCN)5.1 Introduction 5.2 Features 5.3 Functional Description 54 5.4 Block DiagramFigure 5-1 Interrupt Controller Block Diagram 5.5 Operating ModesThe ITCN module design contains two major modes of operation: 55 5.6 Register Descriptions56 Figure 5-2 ITCN Register Map Summary56F8322 Techncial Data, Rev. 10.0 56 Freescale Semiconductor 57 5.6.1 Interrupt Priority Register 0 (IPR0)5.6.1.1 ReservedBits 1514 5.6.1.2 EOnCE Breakpoint Unit 0 Interrupt Priority Level (BKPT_U0 IPL) Bits1312 5.6.1.3 EOnCE Step Counter Interrupt Priority Level (STPCNT IPL) 5.6.1.4 ReservedBits 90 5.6.2 Interrupt Priority Register 1 (IPR1) 58 5.6.3 Interrupt Priority Register 2 (IPR2)5.6.3.5 Low Voltage Detector Interrupt Priority Level (LVI IPL)Bits 76 5.6.3.6 ReservedBits 52 5.6.3.7 External IRQ A Interrupt Priority Level (IRQA IPL)Bits 10 60 5.6.4 Interrupt Priority Register 3 (IPR3)5.6.4.1 ReservedBits 1510 5.6.4.2 FlexCAN Message Buffer Interrupt Priority Level (FCMSGBUF IPL)Bits 98 5.6.4.3 FlexCAN Wake Up Interrupt Priority Level (FCWKUP IPL) Bits 76 5.6.4.4 FlexCAN Error Interrupt Priority Level (FCERR IPL) Bits 54 5.6.4.5 FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL) Bits 32 5.6.4.6 ReservedBits 10 61 5.6.5 Interrupt Priority Register 4 (IPR4)5.6.5.6 GPIO_B Interrupt Priority Level (GPIOB IPL)Bits 32 5.6.5.7 GPIO_C Interrupt Priority Level (GPIOC IPL)Bits 10 63 5.6.6 Interrupt Priority Register 5 (IPR5)Figure 5-8 Interrupt Priority Register 5 (IPR5) 5.6.6.1 ReservedBits 1512 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.6.2 SCI1 Receiver Full Interrupt Priority Level (SCI1_RCV IPL) Bits 1110 65 5.6.7 Interrupt Priority Register 6 (IPR6)5.6.7.1 Timer C, Channel 0 Interrupt Priority Level (TMRC_0 IPL) Bits 1514 5.6.7.2 ReservedBits 134 5.6.7.3 Quadrature Decoder 0, INDEX Pulse Interrupt Priority Level (DEC0_XIRQ IPL)Bits 32 66 5.6.8 Interrupt Priority Register 7 (IPR7)5.6.8.1 Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL) Bits 1514 5.6.8.2 ReservedBits 136 5.6.8.3 Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)Bits 54 5.6.8.4 Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)Bits 32 5.6.8.5 Timer C, Channel 1 Interrupt Priority Level (TMRC1 IPL)Bits 10 67 5.6.9 Interrupt Priority Register 8 (IPR8)5.6.9.1 SCI0 Receiver Full Interrupt Priority Level (SCI0_RCV IPL) Bits 1514 5.6.9.2 SCI0 Receiver Error Interrupt Priority Level (SCI0_RERR IPL) Bits 1312 5.6.9.3 ReservedBits 1110 5.6.9.8 Timer A, Channel 1 Interrupt Priority Level (TMRA1 IPL)Bits 10 69 5.6.10 Interrupt Priority Register 9 (IPR9) 5.6.10.1 PWM A Fault Interrupt Priority Level (PWMAF IPL)Bits 1514 5.6.10.2 ReservedBits 1312 5.6.10.3 Reload PWM A Interrupt Priority Level (PWMA_RL IPL) Bits 1110 5.6.10.4 ReservedBits 98 70 5.6.11 Vector Base Address Register (VBA)71 5.6.12 Fast Interrupt 0 Match Register (FIM0)5.6.12.1 ReservedBits 157 5.6.12.2 Fast Interrupt 0 Vector Number (FAST INTERRUPT 0)Bits 60 5.6.13 Fast Interrupt 0 Vector Address Low Register (FIVAL0) 5.6.13.1 Fast Interrupt 0 Vector Address Low (FIVAL0)Bits 150 5.6.14 Fast Interrupt 0 Vector Address High Register (FIVAH0)5.6.14.1 ReservedBits 155 5.6.14.2 Fast Interrupt 0 Vector Address High (FIVAH0)Bits 40 72 5.6.15 Fast Interrupt 1 Match Register (FIM1)5.6.15.1 ReservedBits 157 5.6.15.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)Bits 60 5.6.16 Fast Interrupt 1 Vector Address Low Register (FIVAL1)5.6.16.1 Fast Interrupt 1 Vector Address Low (FIVAL1)Bits 150 5.6.17 Fast Interrupt 1 Vector Address High Register (FIVAH1)5.6.17.1 ReservedBits 155 5.6.17.2 Fast Interrupt 1 Vector Address High (FIVAH1)Bits 40 73 5.6.18 IRQ Pending 0 Register (IRQP0)5.6.18.1 IRQ Pending (PENDING)Bits 162 5.6.18.2 ReservedBit 0 5.6.19 IRQ Pending 1 Register (IRQP1)5.6.19.1 IRQ Pending (PENDING)Bits 3217 74 5.6.20 IRQ Pending 2 Register (IRQP2)5.6.20.1 IRQ Pending (PENDING)Bits 4833 5.6.21 IRQ Pending 3 Register (IRQP3)5.6.21.1 IRQ Pending (PENDING)Bits 6449 5.6.22 IRQ Pending 4 Register (IRQP4)5.6.22.1 IRQ Pending (PENDING)Bits 8065 75 5.6.23 IRQ Pending 5 Register (IRQP5)5.7 Resets5.7.1 Reset Handshake Timing 5.7.2 ITCN After Reset 77 Part 6 System Integration Module (SIM)93 Part 7 Security Features7.1 Operation with Security Enabled 7.2 Flash Access Blocking Mechanisms 96 Part 8 General Purpose Input/Output (GPIO)8.1 Introduction 8.2 Configuration 8.3 Memory Maps 98 Part 9 Joint Test Action Group (JTAG)99 Part 10 SpecificationsPart 11 Packaging11.1 56F8322 Package and Pin-Out Information PIN 1 Figure 11-1 Top View, 56F8322 48-Pin LQFP Package ORIENTATION MARK 127 Freescale 56F8322129 Freescale 56F8122
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