56F8322 Techncial Data, Rev. 10.0
110 Freescale Semiconductor
Preliminary
10.6 Phase Locked Loop Timing10.7 Oscillator Parameters

Table 10-14 PLL Timing

Characteristic Symbol Min Typ Max Unit
External reference crystal frequency for the PLL1
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
fosc 488MHz
PLL output frequency2 (fOUT)—56F8322
2. ZCLK may not exceed 60MHz. For additional information on ZCLK and (fOUT/2), please refer to the OCCS chapter in the
56F8300 Peripheral User Manual.
fop 160 — 260 MHz
PLL output frequency2 (fOUT)—56F8122 fop 160 — 160 MHz
PLL stabilization time3 -40° to +125°C
3. This is the minimum time req uired after the PLL set up is changed to ensure reliable operation.
tplls —110ms

Table 10-15 Crystal Oscillator Parameters

Characteristic Symbol Min Typ Max Unit
Crystal Start-up time TCS 4510ms
Resonator Start-up time TRS 0.1 0.18 1 ms
Crystal ESR RESR — — 120 ohms
Crystal Peak-to-Peak Jitter TD70 — 250 ps
Crystal Min-Max Period Variation TPV 0.12 — 1.5 ns
Resonator Peak-to-Peak Jitter TRJ — — 300 ps
Resonator Min-Max Period Variation TRP — — 300 ps
Bias Current, high-drive mode IBIASH — 250 290 µA
Bias Current, low-drive mode IBIASL — 80 110 µA
Quiescent Current, power-down mode IPD —01µA