External Clock Operation Timing
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 109
Preliminary
10.5 External Clock Operation Timing

Figure 10-3 External Clock Timing

Table 10-13 External Clock Operation Timing Requirements1
1. Parameters listed are guaranteed by design.
Characteristic Symbol Min Typ Max Unit
Frequency of operation (external clock driver)2—56F8322
2. See Figure 10-3 for details on using the recommended conn ection of an external clock driver.
fosc 0—120MHz
Frequency of operation (external clock driver)2—56F8122 fosc 0—80MHz
Clock Pulse Width3
3. The high or low pulse width mus t be no smaller than 8.0ns or the chip will not function.
tPW 3.0 — — ns
External clock input rise time4
4. External clock input rise time is measured from 10% to 90%.
trise ——15ns
External clock input fall time5
5. External clock input fall time is measured from 90% to 10%.
tfall ——15ns

External

Clock

VIH
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
90%
50%
10%
90%
50%
10%
tPW tPW
tfall trise