56F8322 Techncial Data, Rev. 10.0
66 Freescale Semiconductor
Preliminary
5.6.8 Interrupt Priority Register 7 (IPR7)
Figure 5-10 Interrupt Priority Register (IPR7)

5.6.8.1 Timer A, Channel 0 Interrupt Priority Level (TMRA0 IPL)—

Bits 15–14

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2

5.6.8.2 Reserved—Bits 13–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.8.3 Timer C, Channel 3 Interrupt Priority Level (TMRC3 IPL)—Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2

5.6.8.4 Timer C, Channel 2 Interrupt Priority Level (TMRC2 IPL)—Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.
They are disabled by default.
00 = IRQ disabled (default)
01 = IRQ is priority level 0
10 = IRQ is priority level 1
11 = IRQ is priority level 2
Base + $7 15 14 13 12 11 10 9876543210
Read TMRA0 IPL 00000000TMRC3 IPL TMRC2 IPL TMRC1 IPL
Write
RESET 0000000000000000