Register Descriptions
56F8322 Technical Data, Rev. 10.0
Freescale Semiconductor 85
Preliminary

6.5.7.4 INDEX0 (INDEX)—Bit 7

0 = Peripheral output function of GPIOB[5] is defined to be INDEX0
1 = Peripheral output function of GPIOB[5] is defined to be SYS_CLK

6.5.7.5 HOME0 (HOME)—Bit 6

0 = Peripheral output function of GPIOB[4] is defined to be HOME0
1 = Peripheral output function of GPIOB[4] is defined to be the prescaler clock (FREF, see Figure3-4)

6.5.7.6 Clockout Disable (CLKDIS)—Bit 5

0 = CLKOUT output is enabled and will output the signal indicated by CLKOSEL
1 = CLKOUT is tri-stated

6.5.7.7 CLockout Select (CLKOSEL)—Bits 4–0

Selects clock to be muxed out on the CLKO pin.

00000 = SYS_CLK (from ROCS - DEFAULT)
00001 = Reserved for factory test—56800E clock
00010 = Reserved for factory test—XRAM clock
00011 = Reserved for factory test—PFLASH odd clock
00100 = Reserved for factory test—PFLASH even clock
00101 = Reserved for factory test—BFLASH clock
00110 = Reserved for factory test—DFLASH clock
00111 = MSTR_OSC Oscillator output
01000 = Fout (from OCCS)
01001 = Reserved for factory test—IPB clock
01010 = Reserved for factory test—Feedback (from OCCS, this is path to PLL)
01011 = Reserved for factory test—Prescaler clock (from OCCS)
01100 = Reserved for factory test—Postscaler clock (from OCCS)
01101 = Reserved for factory test—SYS_CLK2 (from OCCS)
01110 = Reserved for factory test—SYS_CLK_DIV2
01111 = Reserved for factory test—SYS_CLK_D
10000 = ADCA clock
6.5.8 SIM GPIO Peripheral Select Register (SIM_GPS)

All of the peripheral pins on the 56F8322 and 56F8122 share their I/O with GPIO ports. To select

peripheral or GPIO control, program the GPIOx_PER register. When SPI 0 and SCI1, Quad Timer C and

SCI 0, or PWMA and SPI 1 are multiplexed, there are two possible peripherals as well as the GPIO

functionality available for control of the I/O. The SIM_GPS register is used to determine which peripheral

has control. The default peripherals are SPI 0, Quad Timer C, and PWMA.