56F8322 Techncial Data, Rev. 10.0
18 Freescale Semiconductor
Preliminary
EXTAL
(GPIOC0)
32 Input/
Schmitt
Input/
Output
Input
Input
External Crystal Oscillator Input — This input can be connected to
an 8MHz external crystal. If an external clock is used, XTAL must be
used as the input and EXTAL connected to VSS.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for the
on-chip PLL.
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is an EXTAL input with pull-ups disabled.
XTAL
(GPIOC1)
33 Output
Schmitt
Input/
Output
Output
Input
Crystal Oscillator Output — This output connects the internal crystal
oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the input and
EXTAL connected to VSS.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for the
on-chip PLL.
Port C GPIO — This GPIO pin can be individually programmed as an
input or output pin.
After reset, the default state is an XTAL input with pull-ups disabled.
TCK 39 Schmitt
Input
Input, pulled
low internally
Test Clock Input — This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/EOnCE
port. The pin is connected internally to a pull-down resis tor. A Schmitt
trigger input is used for noise immunity.
TMS 40 Schmitt
Input
Input, pulled
high
internally
Test Mode Select Input — This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the ris ing edge
of TCK and has an on-chip pull-up resistor.
TDI 41 Schmitt
Input
Input, pulled
high
internally
Test Data Input — This input pin provides a serial input data stream
to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and
has an on-chip pull-up resistor.
TDO 42 Output Tri-stated Test Data Output — This tri-stateable output pin provides a serial
output data stream from the JTAG/EOnCE port. It is driven in the
shift-IR and shift-DR controller states, and changes on the falling edge
of TCK.
Table2-2 Signal and Package Information for the 48-Pin LQFP
Signal Name Pin No. Type State During
Reset Signal Description