Philips TDA8950 manuals
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39 pages 272.13 Kb
1. General description 2. Features 3. Applications TDA8950Rev. 01 9 September 2008 Preliminary data sheet 2 150 W class-D power amplier2 150 W class-D power amplier 2 4. Quick reference data5. Ordering informationPreliminary data sheet Rev. 01 9 September 2008 3 of 39 3 6. Block diagramn.c. VSSA VSSD n.c. IN2M VSSP2VSSP1 The pin numbers in parenthesis refer to type number TDA8950J. Fig 1. Block diagram 4 7. Pinning information7.1 PinningTDA8950TH Fig 2. Pin conguration TDA8950TH Fig 3. Pin conguration TDA8950J NXP Semiconductors TDA8950 7.2 Pin description 5 8. Functional description12 9. Limiting values10. Thermal characteristicsIn accordance with the Absolute Maximum Rating System (IEC 60134). 13 11. Static characteristics = 25 = 35 V; f = 345 kHz; T 14 12. Dynamic characteristics17 13. Application information13.1 Mono BTL application 13.2 Pin MODE 13.3 Output power estimation 13.3.2 Bridge-Tied Load (BTL) 18 13.4 External clock 19 13.5 Noise13.6 Heatsink requirements 20 13.7 Output current limiting23 13.10 Layout and grounding24 13.11 Curves measured in reference designVP = 35 V, 2 4 SE conguration. (1) OUT2, fi = 6 kHz (2) OUT2, fi = 1 kHz (3) OUT2, fi = 100 Hz Fig 13. THD as a function of output power, SE conguration with 2 6 load Fig 12. THD as a function of output power, SE conguration with 2 4 loadVP = 35 V, 2 6 SE conguration. (1) OUT2, fi = 6 kHz (2) OUT2, fi = 1 kHz (3) OUT2, fi = 100 Hz VP = 35 V, fosc = 350 kHz, 1 8 BTL conguration. (1) fi = 6 kHz (2) fi = 1 kHz (3) fi = 100 Hz 25 Fig 14. THD as a function of output power, BTL conguration with 1 8 loadVP = 35 V, 2 4 SE conguration. (1) OUT2, PO = 1 W (2) OUT2, PO = 10 W Fig 15. THD as a function of frequency, SE conguration with 2 4 loadVP = 35 V, 2 6 SE conguration. (1) OUT2, Po = 1 W (2) OUT2, Po = 10 W 26 Fig 16. THD as a function of frequency, SE conguration with 2 6 loadVP = 35 V, 1 8 BTL conguration (1) Po = 1 W (2) Po = 10 W Fig 17. THD as a function of frequency, BTL conguration with 1 8 loadVP = 35 V, 2 4 SE conguration For OUT1 and OUT2 for both 1 W and 10 W. 27 Fig 18. Channel separation as a function of frequency, SE conguration with 2 4loadVP = 35 V, 2 6 SE conguration For OUT1 and OUT2 for both 1 W and 10 W. Fig 19. Channel separation as a function of frequency, SE conguration with 2 6load 28 Fig 20. Power dissipation as function of output power per channelFig 21. Efciency as function of output power per channel 29 Fig 22. Output power as a function of supply voltage, SE congurationFig 23. Output power as function of supply voltage, BTL conguration 30 Fig 24. Gain as function of frequency, Rs = 0 , Ci = 330 pFFig 25. SVRR as function of ripple frequency 31 Fig 26. SVRR as function of ripple frequencyVP = 35 V (1) Out1, down (2) Out1, up Fig 27. Output voltage as function of mode voltageVP = 35 V, Vi = 2 V (rms), fosc = 325 kHz (1) OUT2, 8 (2) OUT2, 6 (3) OUT2, 4 32 Fig 28. Mute attenuation as function of frequency33 14. Package outline35 15. Soldering of SMD packages37 16. Revision historyAN10365 Surface mount reow soldering description 38 17. Legal information17.1 Data sheet status 17.2 Denitions 17.3 Disclaimers 17.4 Trademarks 18. Contact information 39 19. Contents
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