ADC manual Optional, Endian Setting, Little, MLN7400EV, System Clock

1 2 3 4 5

6 7

A

B

OPTIONAL

R1 1M

				X1
XI	R2	33	1	2	R3
			C13	10MHz	C14
			20pF		20pF

GROUNDGROUND

DATA(15:0)

				SYSTEM CLOCK
				VCC_33		TDO			TEST
						TDI		R4	1K
						TCK
33		X2		C184		TMS
	XO
		1		4
			VCC		SYSCLK				GROUND
		NC		0.1uF
		2	OUT	3	R5	33	XI
		GND
		10MHZ				NRESET
	GROUND			GROUND		FILTER	GP42DDATA GP41DMCK CURXD0 CUTXD0		GP40DBCK GP39DLRCK
				ADIN3				XO
	VCC_33A	VCC_33		ADIN0
				ADIN1
				ADIN2

	AGND			144	143	142	141	140	139	138	137	136	135	134	133	132	131	130	129	128	127	126	125	124	123	122	121	120	119	118	117	116	115	114	113	112	111	110	109
			U1
				ADIN3	ADIN2	ADIN1	ADIN0	AVSS33 00	AVDD33 00	AGND33 00	AVREF33	PLLVDD	FILTER	PLLGND	GP42 DDATA	GP41 DMCK	CURXD0	CUTXD0	RESETN	TMS	TCK	TDI	TDO	TEST	XO	XI	GND33 06	VDD33 06	GP40 DBCK	GP39 DLRCK	MDIO	MDC	RX D3	RX D2	RX D1	RX D0	RX DV	RX CLK	RX ERR
7		1	D07

TX_CLK

108

MDIO

MDC

MII_RXD3

MII_RXD2

MII_RXD1

MII_RXD0

MII_RXDV

MII_RXCLK

MII_RXERR

MII_TXCLK

VCC_33

C1	C2	C3	C4	C5	C6	1		TC1
						2
0.1uF	0.1uF	0.1uF	0.1uF	0.1uF	0.1uF		47uF

						GROUND
						VCC_33
C7	C8	C9	C10	C11	C12	1	TC2
						2
0.1uF	0.1uF	0.1uF	0.1uF	0.1uF	0.1uF		47uF

A

B

C

VCC_33

L1

BEADS_100MHz

VCC_33A

C15	1	TC3
0.1uF	2	10uF

6		2	D06
5		3
			D05
4		4
			D04
3		5
			D03
2		6
			D02
1		7
			D01
		8
			VDD33_00
		9	GND33_00
GP27_EXTTCLK0	10		GP27_EXT_TCLK0
	11
GP28_EXTTCLK1			GP28_EXT_TCLK1
0	12		D00
8	13
			D08
9	14
			D09
10	15
			D10

TX_EN

TX_D0

TX_D1

TX_D2

TX_D3 GP38_TOUT3 GP37_TOUT2

RX_COL

RX_CRS GP36_EXINT3 GP35_EXINT2 SDA SCL

GND33_05

107

106

105

104

103

102

101

100

99

98

97

96

95

94

MII_TXEN

MII_TXD0

MII_TXD1

MII_TXD2

MII_TXD3

GP38_TOUT3

GP37_TOUT2

MII_COL

MII_CRS

GP36_EXINT3

GP35_EXINT2 SDA

SCL

		GROUND
R207	0_3216
R204	0_3216	H1
		1
AGND		FHOLE3.5
		GROUND
R206	0_3216
R205	0_3216
		FGND

C

D

GROUND

SDCLK

SDCKE

ADDR(20:0)

C16 820pF

FILTER

GROUND

11		16			D11
	12	17																	MLN7400_144LQFP
					D12
	13	18
					D13
	14	19
					D14
	15	20
					D15
		21
					SDCLK
		22
					CKE
3		23
					AD03
2		24
					AD02
			25
					VDD33_01
				26
					GND33_01
GP29_EXTTCLK2				27	GP29_EXT_TCLK2
		28
GP30_HUARTNDCD4					GP30_HUARTNDCD4
		29
1					AD01
0		30
					AD00
4		31
					AD04
5		32
					AD05
6		33
					AD06
7		34																																							GP33 HUARTNDSR4		GP34 HUARTNDTR4
					AD07																				GP31 HUARTNCTS4		GP32 HUARTNRTS4
8		35
					AD08
																																																	GP00 CUTXD1	GP01 CURXD1	GP02 CUTXD2	GP03 CURXD2	GP04 CUTXD3	GP05 CURXD3	GP06 CUTXD4	GP07 CURXD4 GP08 NBE0
9		36
					AD09										LDQM AD15	UDQM AD16																EAD20 X8EN
						AD10	AD11	AD12	BA0 AD13	BA1 AD14	VDD33 02		GND33 02				SDCSN		RASN		CASN		WEN						EAD17	EAD18	EAD19 BIG		EWEN		EOEN		VDD33 03		GND33 03						ECSN1		ECSN0
					37	38	39	40	41	42		43		44	45	46				48		49		50		51		52	53	54	55	56		57		58		59		60		61		62		63		64	65	66	67	68	69	70	71		72
																		47

VDD33_05 GP26_ENWAIT GP25_IOWR* GP24_IORD* GP23_CE2* GP22_REG* GP21_EXT_UCLK GP20_EXINT1 GP19_EXINT0 GP18_SPICLK GP17_SPIMOSI GP16_SPIMISO GP15_ECSN3 GP14_ECSN2 GP13_NTRST GP12_TX_ERR GP11_TOUT1 GP10_TOUT0 GND33_04 VDD33_04 GP09_NBE1

MLN7400_144LQFP

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

GP08_NBE0 GP07_CURXD4

GP26_ENWAIT GP25_IOWR* GP24_IORD* GP23_CE2* GP22_REG* GP21_EXTUCLK GP20_EXINT1 GP19_EXINT0 GP18_SPICLK GP17_SPIMOSI GP16_SPIMISO GP15_ECSN3 GP14_ECSN2 GP13_NTRST GP12_TXERR GP11_TOUT1 GP10_TOUT0

GP09_NBE1

FGND GROUND

Endian Setting

VCC_33

	SW1 1		BIG
		R6	4.7K
ADDR(19)	2
	3	R7	1K
	4		LITTLE
	5
	6
	SW_DPDT		GROUND

D

E

E

GROUND

SDCSN SDRASN SDCASN SDWEN GP31 HUARTNCTS4 GP32 HUARTNRTS4 NEWE NEOE GP33 HUARTNDSR4 GP34 HUARTNDTR4 NECS1 NECS0

GP06_CUTXD4 GP05_CURXD3 GP04_CUTXD3 GP03_CURXD2 GP02_CUTXD2 GP01_CURXD1 GP00_CUTXD1

DESIGN	CUSTOMER
		MCS LOGIC
CHECK-1			REV.
		MLN7400EV
CHECK-2
DATE	UPDATE	SHEET
2003.11.18		2/14

10 11 12 13 14 15 16 17 18 19 20

1 2 3 4 5

REMARK

Main CPU MLN7400

6