Intel® Server Board SE7520JR2

 

 

Functional Architecture

 

 

 

 

 

 

 

Processor Family

FSB Frequency

Frequency

Support

 

 

Intel® Xeon™

800 MHz

3.2 GHz

Yes

 

 

 

 

 

 

 

 

Intel® Xeon™

800 MHz

3.4 GHz

Yes

 

 

 

 

 

 

 

 

Intel® Xeon™

800 MHz

3.6 GHz

Yes

 

 

 

 

 

 

 

3.1.6.1Processor Mis-population Detection

The processors must be populated in the correct order for the processor front-side bus to be correctly terminated. CPU socket 1 must be populated before CPU socket 2. Baseboard logic will prevent the system from powering up if a single processor is present but it is not in the correct socket. This protects the logic against voltage swings or unreliable operation that could occur on an incorrectly terminated front-side bus.

If processor mis-population is detected when using standard on-board platform instrumentation, the mBMC will log an error against processor 1 to the System Event Log; Configuration Error, and the baseboard hardware will illuminate both processor error LEDs. If an IMM (Professional or Advanced editions) is used in systems, the Sahalee BMC will generate a series of beep codes when this condition is detected and the BMC will illuminate the processor 1 fault LED.

3.1.6.2Mixed Processor Steppings

For optimum system performance, only identical processors should be installed in a system. Processor steppings within a common processor family can be mixed in a system provided that there is no more than a 1 stepping difference between them. If the installed processors are more than 1 stepping apart, an error is reported. Acceptable mixed steppings are not reported as errors by the BIOS.

3.1.6.3Mixed Processor Models

Processor models cannot be mixed in a system. If this condition is detected an error (8196) is logged in the SEL. An example of a faulty processor configuration may be when one installed processor supports a 533MHz front side bus while the other supports an 800MHz front side bus.

3.1.6.4Mixed Processor Families

Processor families cannot be mixed in a system. If this condition is detected an error (8194) is logged in the SEL.

3.1.6.5Mixed Processor Cache Sizes

If the installed processors have mixed cache sizes, an error (8192) will be logged in the SEL and an error (196) is reported to the Management Module. The size of all cache levels must match between all installed processors. Mixed cache processors are not supported.

3.1.6.6Jumperless Processor Speed Settings

The Intel® XeonTM processor does not utilize jumpers or switches to set the processor frequency. The BIOS reads the highest ratio register from all processors in the system. If all processors are the same speed, the Actual Ratio register is programmed with the value read from the High Ratio register. If all processors do not match, the highest common value between

Revision 1.0

29

 

C78844-002