Intel SE7520JR2 3.6Clock Generation and Distribution, 3.5.3.1CONFIG_ADDRESS Register

Intel® Server Board SE7520JR2 Functional Architecture

3.5.3.1CONFIG_ADDRESS Register

CONFIG_ADDRESS is 32 bits wide and contains the field format shown in the following figure. Bits [23::16] choose a specific bus in the system. Bits [15::11] choose a specific device on the selected bus. Bits [10:8] choose a specific function in a multi-function device. Bit [7::1] select a specific register in the configuration space of the selected device or function on the bus.

3.6Clock Generation and Distribution

All buses on the baseboard operate using synchronous clocks. Clock synthesizer/driver circuitry on the baseboard generates clock frequencies and voltage levels as required, including the following:

•200MHz differential clock at 0.7V logic levels. For Processor 0, Processor 1, Debug Port and MCH.

•100MHz differential clock at 0.7V logic levels on CK409B. For DB800 clock buffer.

•100MHz differential clock at 0.7 Vlogic levels on DB800. For PCI Express Device it is the MCH, PXH and full-length riser, which includes x4 PCI Express Slot. For SATA it is the ICH5-R.

•66MHz at 3.3V logic levels: For MCH and ICH5-R.

•48MHz at 3.3V logic levels: For ICH5-R and SIO.

•33MHz at 3.3V logic levels: For ICH5-R, Video, BMC and SIO.

•14.318MHz at 2.5V logic levels: For ICH5-R and video.

•10Mhz at 5V logic levels: For mBMC.

The PCI-X slot speed on the full-length riser card and on the low-profile riser card is determined by the riser card in use.

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