Intel SE7520JR2 manual Main Memory, PCI Memory Space, High Bios, High Memory Gap Reclaiming

Functional Architecture Intel® Server Board SE7520JR2

3.5.1.2.1Main Memory

All installed memory greater than 1MB is mapped to local main memory, up to 8GB of physical memory. Memory between 1MB to 15MB is considered to be standard ISA extended memory. 1MB of memory starting at 15MB can be optionally mapped to the PCI bus memory space.

The remainder of this space, up to 8GB, is always mapped to main memory, unless TBSG SMM is used which is just under TOLM. The range can be from 128KB till 1MB. 1MB depends on the BIOS setting C SMRAM is used which limits the top of memory to 256MB. The BIOS occupies 512KB for the 32-bit SMI handler.

3.5.1.2.2PCI Memory Space

Memory addresses below the 4GB range are mapped to the PCI bus. This region is divided into three sections: High BIOS, APIC configuration space, and general-purpose PCI memory. The General-purpose PCI memory area is typically used memory-mapped I/O to PCI devices. The memory address space for each device is set using PCI configuration registers.

3.5.1.2.3High BIOS

The top 1MB of extended memory under 4GB is reserved for the system BIOS, extended BIOS for PCI devices, and A20 aliasing by the system BIOS. The lntel Xeon processor begins executing from the high BIOS region after reset.

3.5.1.2.4High Memory Gap Reclaiming

The BIOS creates a region immediately below 4 GB to accommodate memory-mapped I/O regions for the system BIOS Flash, APIC memory and 32-bit PCI devices. Any system memory in this region is remapped above 4GB.

3.5.1.2.5I/O APIC Configuration Space

A 64KB block located 20MB below 4GB (0FEC00000 to 0FEC0FFFFh) is reserved for the I/O APIC configuration space. The first I/O APIC is located at FEC00000h. The second I/O APIC is located at FEC80000h. The third I/O APIC is located at FEC80100h.

3.5.1.2.6Extended lntel® Xeon™ Processor Region (above 4GB)

An lntel Xeon processor based system can have up to 64 GB of addressable memory. With the chipset only supporting 16GB of addressable memory, the BIOS uses an extended addressing mechanism to use the address ranges.

3.5.1.3Memory Shadowing

System BIOS and option ROM can be shadowed in main memory. Typically this is done to allow ROM code to execute more rapidly out of RAM. ROM is designated read-only during the copy process while RAM at the same address is designated write-only. After copying, the RAM is designated read-only. After the BIOS is shadowed, the attributes for that memory area are set to read only so that all writes are forwarded to the expansion bus.

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