Table of Contents

Intel® Server Board SE7520JR2

5.1

Platform Management Architecture Overview

115

5.1.1

5V Standby

116

5.1.2

IPMI Messaging, Commands, and Abstractions xxx

116

5.1.3

IPMI ‘Sensor Model’

117

5.1.4

Private Management Busses

118

5.1.5

Management Controllers

118

5.2

On-Board Platform Management Features and Functionality

.............................. 121

5.2.1

Server Management I2C Buses

122

5.2.2

Power Control Interfaces

122

5.2.3

External Interface to the mBMC

122

5.3

mBMC Hardware Architecture

123

5.3.1

Power Supply Interface Signals

124

5.3.2

Power Control Sources

126

5.3.3

Power-up Sequence

126

5.3.4

Power-down Sequence

126

5.3.5

System Reset Control

126

5.3.5.1

 

Reset Signal Output

126

5.3.5.2

 

Reset Control Sources

127

5.3.5.3 Control Panel System Reset

127

5.3.5.4

 

Control Panel Indicators

128

5.3.5.5

 

Control Panel Inputs

129

5.3.6

Secure Mode Operation

131

5.3.7

Baseboard Fan Control

131

5.3.8

mBMC Peripheral SMBus

131

5.3.9

Watchdog Timer

131

5.3.10

System Event Log (SEL)

131

5.3.10.1

SEL Erasure

132

5.3.10.2

Timestamp Clock

132

5.3.11

Sensor Data Record (SDR) Repository

132

5.3.11.1

Initialization Agent

132

5.3.12

Field Replaceable Unit (FRU) Inventory Devices

133

5.3.12.1 mBMC FRU Inventory Area Format

133

5.3.13

NMI Generation

133

5.3.14

SMI Generation

133

5.3.15

Event Message Reception

133

5.3.16

mBMC Self Test

134

5.3.17

Messaging Interfaces

134

5.3.17.1

Channel Management

134

 

 

 

 

 

viii

 

C78844-002

 

Revision 1.0

 

 

 

 

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Intel SE7520JR2 manual Viii C78844-002