Intel® Server Board SE7520JR2

Functional Architecture

3.1Processor Sub-system

The support circuitry for the processor sub-system consists of the following:

•Dual 604-pin zero insertion force (ZIF) processor sockets

•Processor host bus AGTL+ support circuitry

•Reset configuration logic

•Processor module presence detection logic

•BSEL detection capabilities

•CPU signal level translation

•Common Enabling Kit (CEK) CPU retention support

3.1.1Processor Voltage Regulators

The baseboard has two VRDs (Voltage Regulator Devices) providing the appropriate voltages to the installed processors. Each VRD is compliant with the VRD 10.1 specification and is designed to support Intel® Xeon™ processors that require up to a sustained maximum of 105 AMPs and peak support of 120A.

The baseboard supports the current requirements and processor speed requirements defined in the Flexible Mother Board (FMB) specification for all 800 MHz FSB Intel Xeon processors. FMB is an estimation of the maximum values the 800 MHz FSB versions of the Intel Xeon processors will have over their lifetime. The value is only an estimate and actual specifications for future processors may differ. At present, the current demand per FMB is a sustained maximum of a 105 Amps and peak support of 120 Amps.

3.1.2Reset Configuration Logic

The BIOS determines the processor stepping, cache size, etc through the CPUID instruction. All processors in the system must operate at the same frequency; have the same cache sizes; and same VID. No mixing of product families is supported. Processors run at a fixed speed and cannot be programmed to operate at a lower or higher speed.

3.1.3Processor Module Presence Detection

Logic is provided on the baseboard to detect the presence and identity of installed processors. In dual-processor configurations, the on-board mini Baseboard Management Controller (mBMC) must read the processor voltage identification (VID) bits for each processor before turning on the VRD. If the VIDs of the two processors are not identical, then the mBMC will not turn on the VRD. Prior to enabling the embedded VRD, circuitry on the baseboard ensures that the following criteria are met:

•In a uni-processor configuration, CPU 1 is installed

•Only supported processors are installed in the system to prevent damage to the MCH

•In dual processor configurations, both processors support the same FSB frequency

3.1.4GTL2006

The GTL2006 is a 13-bit translator designed for 3.3V to GTL/GTL+ translations to the system bus. The translator incorporates all the level shifting and logic functions required to interface between the processor subsystem and the rest of the system.

Revision 1.0

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C78844-002