Table of ContentsIntel® Server Board SE7520JR2Table of Contents

1.

Introduction ........................................................................................................................

19

 

 

1.1

Chapter Outline......................................................................................................

19

 

 

1.2

Server Board Use Disclaimer ................................................................................

20

2.

Server Board Overview......................................................................................................

21

 

 

2.1

Server Board SE7520JR2 SKU Availability ...........................................................

21

 

 

2.2

Server Board SE7520JR2 Feature Set..................................................................

21

3.

Functional Architecture .....................................................................................................

26

 

 

3.1

Processor Sub-system...........................................................................................

27

 

 

3.1.1

Processor Voltage Regulators ...............................................................................

27

 

 

3.1.2

Reset Configuration Logic .....................................................................................

27

 

 

3.1.3

Processor Module Presence Detection .................................................................

27

 

 

3.1.4

GTL2006................................................................................................................

27

 

 

3.1.5

Common Enabling Kit (CEK) Design Support........................................................

28

 

 

3.1.6

Processor Support .................................................................................................

28

 

 

3.1.6.1

 

Processor Mis-population Detection ..................................................................

29

 

 

3.1.6.2

 

Mixed Processor Steppings ...............................................................................

29

 

 

3.1.6.3

 

Mixed Processor Models....................................................................................

29

 

 

3.1.6.4

 

Mixed Processor Families ..................................................................................

29

 

 

3.1.6.5 Mixed Processor Cache Sizes ...........................................................................

29

 

 

3.1.6.6 Jumperless Processor Speed Settings ..............................................................

29

 

 

3.1.6.7

 

Microcode...........................................................................................................

30

 

 

3.1.6.8

 

Processor Cache................................................................................................

30

 

 

3.1.6.9

 

Hyper-Threading Technology.............................................................................

30

 

 

3.1.6.10

Intel® SpeedStep® Technology.......................................................................

30

 

 

3.1.6.11

EM64T Technology Support ............................................................................

30

 

 

3.1.7

Multiple Processor Initialization .............................................................................

30

 

 

3.1.8

CPU Thermal Sensors...........................................................................................

31

 

 

3.1.9

Processor Thermal Control Sensor .......................................................................

31

 

 

3.1.10

Processor Thermal Trip Shutdown ........................................................................

31

 

 

3.1.11

Processor IERR .....................................................................................................

31

 

 

3.2

Intel® E7520 Chipset.............................................................................................

31

 

 

3.2.1

Memory Controller Hub (MCH) ..............................................................................

32

 

 

3.2.1.1 Front Side Bus (FSB) .........................................................................................

32

 

 

3.2.1.2 MCH Memory Sub-System Overview.................................................................

32

 

 

3.2.1.3

 

PCI Express .......................................................................................................

32

 

 

3.2.1.4

 

Hub Interface......................................................................................................

33

 

 

 

 

 

 

 

iv

 

 

C78844-002

Revision 1.0