Intel® Server Board SE7520JR2

List of Figures
List of Figures

 

Figure 1. SE7520JR2 Board Layout ...........................................................................................

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Figure 2. Server Board Dimensions............................................................................................

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Figure 3. Server Board SE7520JR2 Block Diagram ...................................................................

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Figure 4. CEK Processor Mounting ............................................................................................

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Figure 5. Identifying Banks of Memory .......................................................................................

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Figure 6. Four DIMM Memory Mirror Configuration ....................................................................

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Figure 7. Six DIMM Memory Mirror Configuration (DDR2 Only) .................................................

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Figure 8. Interrupt Routing Diagram (ICH5-R Internal) ...............................................................

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Figure 9. Interrupt Routing Diagram ...........................................................................................

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Figure 10. PCI Interrupt Mapping Diagram .................................................................................

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Figure 11. PCI Interrupt Mapping Diagram for 2U Active Riser Card .........................................

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Figure 12. Serial Port Mux Logic.................................................................................................

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Figure 13. RJ45 Serial B Port Jumper Block Location and Setting.............................................

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Figure 14. Intel® Xeon™ Processor Memory Address Space.....................................................

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Figure 15. DOS Compatibility Region .........................................................................................

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Figure 16. Extended Memory Map..............................................................................................

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Figure 17. BIOS Identification String...........................................................................................

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Figure 18. POST Console Interface............................................................................................

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Figure 19. On-Board Platform Management Architecture.........................................................

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Figure 20. mBMC in a Server Management System.................................................................

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Figure 21. External Interfaces to mBMC...................................................................................

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Figure 22. mBMC Block Diagram .............................................................................................

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Figure 23. Power Supply Control Signals .................................................................................

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Figure 24. Location of Diagnostic LEDs on Baseboard ............................................................

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Figure 25. 34-Pin SSI Compliant Control Panel Header...........................................................

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Figure 26. System Configuration (J1H2) Jumper Block Settings..............................................

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Figure 27. Power Harness Specification Drawing.....................................................................

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Figure 28. Output Voltage Timing .............................................................................................

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Figure 29. Turn On/Off Timing (Power Supply Signals)............................................................

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Revision 1.0

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C78844-002