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Intel SE7520JR2 5.1Platform Management Architecture Overview, SIO, PC87427, C78844-002, Intel® Server Board SE7520JR2, Figure 19. On-BoardPlatform Management Architecture

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Intel® Server Board SE7520JR2

Platform Management

5.1Platform Management Architecture Overview

CPU1

LM 93

VID_CPU0[5:0]	P1_VID[5:0]	ProcHot				CPU2
VID_CPU0[5:0]	P1_VID[5:0]
VID_CPU1[5:0]		ThermTrip
VID_CPU1[5:0]	P2_VID[5:0]	ThermTrip
Not Used	+12V1
P12V_CPU_SCALED	+12V1
P12V_CPU_SCALED	+12V2	IERR
P12V_SCALED	+12V2	IERR
P_VTT	+12V3
P_VTT	FSB_Vtt
P1V5	FSB_Vtt
Not Used	Chipset_Core
P_VCCP0	ICH_Core		Zone 1
P_VCCP1	CPU1_Vccp	PWM1	Zone 1
P3V3	CPU2_Vccp	PWM1
P5V	3.3V		Zone2
P1V8_SCSI	+5V	PWM2	Zone2
DDRCore	SCSI_Core	PWM2
DDRVtt	Mem_Core
DDRVtt	Mem_Vtt
GbLAN Core	Mem_Vtt
N12V_SCALED	GBIT_Core		CPU	CPU	Fan	Fan
P3V3_STBY	-12V		CPU	CPU	Fan	Fan
	+3.3S/B Vcc		Fan	Fan
SCSIA_TERMPWR	SCSI_term1		Fan	Fan
SCSIB_TERMPWR	SCSI_term1
SCSIB_TERMPWR	SCSI_term2	Tach1
	SCSI_term2

Config

Check Logic

PC87431 mBMC

CPU1Thermal Diode	RTD(1)	Tach2

CPU2Thermal Diode RTD(2)

Tach3

Tach4

Fan Fan

PC87427SIO

FANIN1

FANIN2

Mem

FANIN3 Fan

1WIREBusTemp

CHASSISINTRUSION

Chassis

Security SECURE_MODE_KB

LEDPWR_LED

Connector Panel Front

CPU_CFG_ERR_N

FP_ID_BTN_N

FP_RST_BTN

FP_PWR_BTN

FP_NMI_BTN

FP_ID_LED_N

FP_SYS_FLT_LED_A FP_SYS_FLT_LED_C

SECURE_MODE_KB FRB3_TMR_HALT_N PS_PWR_GD

CPU1_SEL

CPU2_SEL

ICH_RST_BTN ICH_PWR_BTN

SYS_NMI

SYS_SMI

Figure 19. On-Board Platform Management Architecture

Revision 1.0	115
	C78844-002

Contents

Revision October Enterprise Platforms and Services Marketing Revision History Disclaimers Table of ContentsIntel® Server Board SE7520JR2 Table of Contents Page Page Page Page Page Page Page Appendix A: Integration and Usage Tips List of Figures List of Figures List of Tables List of Tables Page Page Page < This page intentionally left blank 1.Introduction 1.1Chapter Outline 1.2Server Board Use Disclaimer 2.Server Board Overview 2.1Server Board SE7520JR2 SKU Availability 2.2Server Board SE7520JR2 Feature Set Page Page Table 1: Baseboard Layout Reference Page 3.Functional Architecture 3.1Processor Sub-system 3.1.1Processor Voltage Regulators 3.1.2Reset Configuration Logic 3.1.3Processor Module Presence Detection 3.1.4GTL2006 3.1.5Common Enabling Kit (CEK) Design Support 3.1.6Processor Support 3.1.6.1Processor Mis-populationDetection 3.1.6.2Mixed Processor Steppings 3.1.6.3Mixed Processor Models 3.1.6.4Mixed Processor Families 3.1.6.5Mixed Processor Cache Sizes 3.1.7Multiple Processor Initialization 3.1.8CPU Thermal Sensors 3.1.9Processor Thermal Control Sensor 3.1.10Processor Thermal Trip Shutdown 3.1.11Processor IERR 3.2Intel® E7520 Chipset 3.2.1Memory Controller Hub (MCH) 3.2.2PCI-XHub (PXH) 3.2.3I/O Controller Hub (ICH5-R) 3.2.3.3SATA Controller 3.2.3.4Low Pin Count (LPC) Interface Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) 3.2.3.6Advanced Programmable Interrupt Controller (APIC) 3.2.3.7Universal Serial Bus (USB) Controller 3.2.3.8RTC 3.2.3.9General Purpose I/O (GPIO) 3.2.3.10Enhanced Power Management 3.3Memory Sub-System 3.3.1Memory Sizing MCH 3.3.2Memory Population DDR-266& DDR-333DIMM population rules are as follows: DDR2 400 DIMM population rules are as follows: 3.3.3ECC Memory Initialization 3.3.4Memory Test 3.3.5Memory Monitoring 3.3.6Memory RASUM Features 3.3.6.3Retry on Uncorrectable Error 3.3.6.4Integrated Memory Initialization Engine 3.3.6.5DIMM Sparing Function 3.3.6.6Memory Mirroring This configuration is only valid with DDR2 memory Page 3.4I/O Sub-System 3.4.1PCI Subsystem 3.4.1.1P32-A: 32-bit, 33-MHzPCI Subsystem 3.4.1.2P64-Aand P64-B: 64-bit,100MHz PCI Subsystem 3.4.1.3P64-Express:Dual x4 PCI Bus Segment 3.4.1.4PCI Riser Slots 3.4.1.5PCI Scan Order 3.4.1.6PCI Bus Numbering 3.4.1.7Device Number and IDSEL Mapping Table 8: PCI Configuration IDs and Device Numbers 3.4.2Split Option ROM 3.4.3Interrupt Routing 3.4.3.2APIC Interrupt Routing 3.4.3.3Legacy Interrupt Sources Table 10: Interrupt Definitions 3.4.3.4Serialized IRQ Support 3.4.3.5IRQ Scan for PCIIRQ Page Page 3.4.4SCSI Support Page 3.4.5IDE Support 3.4.6SATA Support 3.4.7Video Support Table 11: Video Modes 3.4.7.2Video Memory Interface Table 12: Video Memory Interface 3.4.8Network Interface Controller (NIC) 3.4.9USB 2.0 Support 3.4.10Super I/O Chip Page 3.4.10.2Serial Ports 3.4.10.2.1Serial Port A 3.4.10.2.2Serial Port B 3.4.10.2.3Serial Port Multiplexer Logic 3.4.10.2.4Rear RJ45 Serial B Port Configuration 3.4.11BIOS Flash 3.5Configuration and Initialization 3.5.1Memory Space 3.5.1.1DOS Compatibility Region Figure 15. DOS Compatibility Region 3.5.1.1.1DOS Area 3.5.1.1.2ISA Window Memory 3.5.1.1.3Video or SMM Memory 3.5.1.1.4Add-inCard BIOS and Buffer Area 3.5.1.1.5Extended System BIOS 3.5.1.2Extended Memory Figure 16. Extended Memory Map 3.5.1.2.1Main Memory 3.5.1.2.2PCI Memory Space 3.5.1.2.3High BIOS 3.5.1.2.4High Memory Gap Reclaiming 3.5.1.2.5I/O APIC Configuration Space 3.5.1.4System Management Mode Handling 3.5.2I/O Map Page 3.5.3Accessing Configuration Space 3.6Clock Generation and Distribution 4.System BIOS 4.1BIOS Identification String 4.2Flash Architecture and Flash Update Utility 4.3BIOS Power On Self Test (POST) 4.3.1User Interface 4.3.1.1System Activity Window 4.3.1.2Splash Screen/Diagnostic Window 4.3.1.2.1System Diagnostic Screen 4.3.2BIOS Boot Popup Menu 4.4BIOS Setup Utility 4.4.1Localization 4.4.2Entering BIOS Setup 4.4.2.2Advanced Menu Table 20: BIOS Setup, Advanced Menu Options 4.4.2.2.1Processor Configuration Sub-menu Table 21: BIOS Setup, Processor Configuration Sub-menuOptions 4.4.2.2.2IDE Configuration Sub-menu Table 22: BIOS Setup IDE Configuration Menu Options Table 23: Mixed P-ATA-S-ATAConfiguration with only Primary P-ATA Table 24: BIOS Setup, IDE Device Configuration Sub-menuSelections 4.4.2.2.3Floppy Configuration Sub-menu Table 25: BIOS Setup, Floppy Configuration Sub-menuSelections 4.4.2.2.4Super I/O Configuration Sub-menu Table 26: BIOS Setup, Super I/O Configuration Sub-menu 4.4.2.2.5USB Configuration Sub-menu Table 27: BIOS Setup, USB Configuration Sub-menuSelections a.USB Mass Storage Device Configuration Sub-menu Table 28: BIOS Setup, USB Mass Storage Device Configuration Sub-menuSelections 4.4.2.2.6PCI Configuration Sub-menu Table 29: BIOS Setup, PCI Configuration Sub-menuSelections 4.4.2.2.7Memory Configuration Sub-menu Table 30: BIOS Setup, Memory Configuration Sub-menuSelections 4.4.2.3Boot Menu Table 31: BIOS Setup, Boot Menu Selections 4.4.2.3.1Boot Settings Configuration Sub-menuSelections Table 32: BIOS Setup, Boot Settings Configuration Sub-menuSelections 4.4.2.3.2Boot Device Priority Sub-menuSelections Table 33: BIOS Setup, Boot Device Priority Sub-menuSelections Hard Disk Drive Sub-menuSelections Table 34: BIOS Setup, Hard Disk Drive Sub-MenuSelections Removable Drive Sub-menuSelections 4.4.2.4Security Menu Table 37: BIOS Setup, Security Menu Options 4.4.2.5Server Menu Table 38: BIOS Setup, Server Menu Selections 4.4.2.5.1System Management Sub-menuSelections Table 39: BIOS Setup, System Management Sub-menuSelections 4.4.2.5.2Serial Console Features Sub-menuSelections Table 40: BIOS Setup, Serial Console Features Sub-menuSelections 4.4.2.5.3Event Log Configuration Sub-menuSelections Table 41: BIOS Setup, Event Log Configuration Sub-menuSelections 4.5Rolling BIOS and On-lineUpdates 4.5.1Flash Update Utility 4.5.2.Configuration Reset 4.6OEM Binary 4.7Security 4.7.1Operating Model Notes: Scenario #1 Scenario #2 Scenario #3 4.7.2Password Clear Jumper 4.8Extensible Firmware Interface (EFI) 4.8.1EFI Shell 4.9Operating System Boot, Sleep, and Wake 4.9.1Microsoft* Windows* Compatibility 4.9.2Advanced Configuration and Power Interface (ACPI) 4.9.2.2Power Switch Off to On 4.9.2.3On to Off (OS absent) 4.9.2.4On to Off (OS present) 4.9.2.5On to Sleep (ACPI) 4.9.2.6Sleep to On (ACPI) 4.9.2.7System Sleep States 4.10 PXE BIOS Support 4.11 Console Redirection 5.Platform Management Page 5.1Platform Management Architecture Overview 5.1.15V Standby 5.1.2IPMI Messaging, Commands, and Abstractions 5.1.3IPMI ‘Sensor Model’ 5.1.4Private Management Busses 5.1.5Management Controllers Page Page 5.2On-BoardPlatform Management Features and Functionality 5.2.1Server Management I2C Buses 5.2.2Power Control Interfaces 5.2.3External Interface to the mBMC 5.3mBMC Hardware Architecture 5.3.1Power Supply Interface Signals Page 5.3.2Power Control Sources 5.3.3Power-upSequence 5.3.4Power-downSequence 5.3.5System Reset Control 5.3.5.2Reset Control Sources Table 48: System Reset Sources and Actions 5.3.5.3Control Panel System Reset •Power button assertion •Reset button assertion •Combined power and reset button assertion 5.3.5.4Control Panel Indicators 5.3.5.4.1Power LED 5.3.5.4.2Fault / Status LED Critical Condition Non-CriticalCondition Degraded Condition 5.3.5.4.3Chassis ID LED 5.3.5.5.1Chassis Intrusion 5.3.5.5.2Power Button 5.3.5.5.3Reset Button 5.3.5.5.4Diagnostic Interrupt Button (Control Panel NMI) 5.3.5.5.5Chassis Identify Button 5.3.6Secure Mode Operation 5.3.7Baseboard Fan Control 5.3.8mBMC Peripheral SMBus 5.3.9Watchdog Timer 5.3.10System Event Log (SEL) 5.3.11Sensor Data Record (SDR) Repository 5.3.12Field Replaceable Unit (FRU) Inventory Devices 5.3.13NMI Generation 5.3.14SMI Generation 5.3.15Event Message Reception 5.3.16mBMC Self Test 5.3.17Messaging Interfaces 5.3.17.5LAN Interface 5.3.18Event Filtering and Alerting 5.3.19mBMC Sensor Support Table 55: Platform Sensors for On-BoardPlatform Instrumentation Page Page Page 5.3.20IMM BMC Sensor Support Page Page Page Page Page 5.4Wired For Management (WFM) 5.5Vital Product Data (VPD) 5.6System Management BIOS (SMBIOS) 6.Error Reporting and Handling 6.1Fault Resilient Booting (FRB) 6.1.1FRB1 – BSP Self-TestFailures 6.1.2FRB2 – BSP POST Failures 6.1.3FRB3 – BSP Reset Failures 6.1.4OS Watchdog Timer - Operating System Load Failures 6.1.5AP Failures 6.1.6Treatment of Failed Processors 6.2Memory Error Handling 6.2.1Memory Error Handling in RAS Mode 6.2.2Memory Error Handling in non-RASMode 6.2.3DIMM Enabling 6.2.4Single-bitECC Error Throttling Prevention 6.3Error Logging 6.3.1SMI Handler 6.3.2PCI Bus Error 6.3.3Processor Bus Error 6.3.4Memory Bus Error 6.4Error Messages and Error Codes 6.4.1POST Error Messages Table 60: Boot BIOS Messages Table 61: Storage Device BIOS Messages Page Page Table 62: Virus Related BIOS Messages Table 63: System Configuration BIOS Messages Table 64: CMOS BIOS Messages Table 65: Miscellaneous BIOS Messages Table 66: USB BIOS Error Messages 6.4.2POST Error Codes Page Table 69: Error Codes Sent to the Management Module 6.4.3BIOS Generated POST Error Beep Codes 6.4.4Boot Block Error Beep Codes 6.4.5BMC Generated Beep Codes (Professional/Advanced only) 6.5Checkpoints 6.5.1System ROM BIOS POST Task Test Point (Port 80h Code) 6.5.2Diagnostic LEDs 6.5.3POST Code Checkpoints Page 6.5.4Bootblock Initialization Code Checkpoints 6.5.5Bootblock Recovery Code Checkpoint 6.5.6DIM Code Checkpoints 6.5.7ACPI Runtime Checkpoints 6.5.8POST Progress FIFO (Professional / Advanced only) 6.5.9Memory Error Codes 6.6Light Guided Diagnostics 7.Connectors and Jumper Blocks 7.1Power Connectors 7.2Riser Slots 7.2.1Low Profile PCI-XRiser Slot Page Page 7.2.2Full Height PCI-XRiser Slot Table 86: Full-heightRiser Slot Pinout Page Page Page 7.3System Management Headers 7.3.1Intel® Management Module Connector Page Page 7.3.2ICMB Header 7.3.3IPMB Header Table 89: IPMB Connector Pin-out(J3F1) 7.3.4OEM RMC Connector (J3B2) 7.4Control Panel Connectors Table 92: 50-PinControl Panel Connector (Intel Chassis w/No Backplane) (J1J2) Table 93: Control Panel SSI Standard 34-PinHeader Pin-out 7.5I/O Connectors 7.5.1VGA Connector 7.5.2NIC Connectors 7.5.3SCSI Connectors 7.5.4ATA-100Connector 7.5.5SATA Connectors 7.5.6Floppy Controller Connector 7.5.7Serial Port Connectors 7.5.8Keyboard and Mouse Connector 7.5.9USB Connector 7.6Fan Headers Table 106: CPU1/CPU2 Fan Connector Pin-out(J5F2, J7F1) Table 107: Intel Server Chassis Fan Header Pin-out(J3K6) 7.7Misc. Headers and Connectors 7.7.1Chassis Intrusion Header 7.7.2Hard Drive Activity LED Header 7.8Jumper Blocks 8.Design and Environmental Specifications 8.1Server Board SE7520JR2 Design Specification 8.2Power Supply Requirements 8.2.1Output Connectors Figure 27. Power Harness Specification Drawing P1 Main Power Connector Table 113: P1 Main Power Connector P2 Processor Power Connector Table 114: P2 Processor Power Connector 8.2.2Grounding 8.2.3Remote Sense 8.2.4Standby Outputs 8.2.5Voltage Regulation 8.2.6Dynamic Loading 8.2.7Capacitive Loading 8.2.8Closed Loop Stability 8.2.9Common Mode Noise 8.2.10Ripple / Noise 8.2.11Soft Starting 8.2.12Zero Load Stability Requirements 8.2.13Timing Requirements Figure 28. Output Voltage Timing Table 123: Turn On/Off Timing 8.2.14Residual Voltage Immunity in Standby Mode 8.3Product Regulatory Compliance 8.3.1Product Safety Compliance 8.3.2Product EMC Compliance – Class A Compliance 8.3.3Certifications / Registrations / Declarations 8.3.4Product Regulatory Compliance Markings 8.4Electromagnetic Compatibility Notices 8.4.1FCC (USA) 8.4.2Industry Canada (ICES-003) 8.4.3Europe (CE Declaration of Conformity) 8.4.4Taiwan Declaration of Conformity (BSMI) 8.4.5Korean Compliance (RRL) 9.Miscellaneous Board Information 9.1Updating the System Software 9.2Programming FRU and SDR Data 9.3Clearing CMOS 9.3.1CMOS Clear Using J1H2 Jumper Block 9.3.2CMOS Clear using Control Panel 9.4BIOS Recovery Operation Page Page Appendix A: Integration and Usage Tips Glossary Page Page Reference Documents