Functional Architecture

Intel® Server Board SE7520JR2

3.2.2.3I/OxAPIC Controller

The PXH contains two I/OxAPIC controllers, both of which reside on the primary bus. The intended use of these controllers is to have the interrupts from PCI bus A connected to the interrupt controller on device 0, function 1 and have the interrupts on PCI bus B connected to the interrupt controller on device 0, function 3.

3.2.2.4SMBus Interface

The SMBus interface can be used for system and power management related tasks. The interface is compliant with System Management Bus Specification Revision 2.0. The SMBus interface allows full read/write access to all configuration and memory spaces in the PXH.

3.2.3I/O Controller Hub (ICH5-R)

The ICH5-R is a multi-function device providing an upstream hub interface for access to several embedded I/O functions and features including:

•PCI Local Bus Specification, Revision 2.3 with support for 33 MHz PCI operations.

•ACPI power management logic support

•Enhanced DMA controller, interrupt controller, and timer functions

•Integrated IDE controller with support for Ultra ATA100/66/33

•Integrated SATA controller

•USB host interface with support for eight USB ports; four UHCI host controllers; one EHCI high-speed USB 2.0 host controller

•System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices

•Low Pin Count (LPC) interface

•Firmware Hub (FWH) interface support

Each function within the ICH5-R has its own set of configuration registers. Once configured, each appears to the system as a distinct hardware controller sharing the same PCI bus interface.

3.2.3.1PCI Interface

The ICH5-R PCI interface provides a 33 MHz, Revision 2.3 compliant implementation. All PCI signals are 5-V tolerant, except PME#. The ICH5 integrates a PCI arbiter that supports up to six external PCI bus masters in addition to the internal ICH5 requests. On the Server Board SE7520JR2 this PCI interface is used to support on-board PCI devices including the ATI* video controller, Super I/O chip, and hardware monitoring sub-system.

3.2.3.2IDE Interface (Bus Master Capability and Synchronous DMA Mode)

The fast IDE interface supports up to four IDE devices, providing an interface for IDE hard disks and ATAPI devices. Each IDE device can have independent timings. The IDE interface supports PIO IDE transfers up to 16 Mbytes/sec and Ultra ATA transfers up 100 Mbytes/sec. It does not consume ISA DMA resources. The IDE interface integrates 16x32-bit buffers for optimal transfers. The ICH5-R’s IDE system contains two independent IDE signal channels. They can be electrically isolated independently. They can be configured to the standard primary and secondary channels (four devices). The Server Board SE7520JR2 provides interfaces to both

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Revision 1.0

 

C78844-002