Intel SE7520JR2 manual Advanced Programmable Interrupt Controller Apic, 3.8 RTC

Functional Architecture Intel® Server Board SE7520JR2

3.2.3.6Advanced Programmable Interrupt Controller (APIC)

In addition to the standard ISA-compatible PIC described in the previous section, the ICH5-R incorporates the Advanced Programmable Interrupt Controller (APIC).

3.2.3.7Universal Serial Bus (USB) Controller

The ICH5-R contains an Enhanced Host Controller Interface (EHCI) for Universal Serial Bus, Revision 1.0-compliant host controller that supports USB high-speed signaling. The high-speed USB 2.0 allows data transfers up to 480 Mb/s, which is 40 times faster than full-speed USB.

The ICH5-R also contains four Universal Host Controller Interface (UHCI) controllers that support USB full-speed and low-speed signaling. On the Server Board SE7520JR2, the ICH5-R provides six USB 2.0 ports. All six ports are high-speed, full-speed, and low-speed capable. ICH5-R’s port-routing logic determines whether a USB port is controlled by one of the UHCI controllers or by the EHCI controller.

3.2.3.8RTC

The ICH5-R contains a Motorola* MC146818A-compatible real-time clock with 256 bytes of battery backed RAM. The real-time clock performs two key functions: keeping track of the time of day and storing system data, even when the system is powered down. The RTC operates on a 32.768 KHz crystal and a separate 3 V lithium battery.

The RTC supports two lockable memory ranges. By setting bits in the configuration space, two 8-byte ranges can be locked to read and write accesses. This prevents unauthorized reading of passwords or other system security information.

The RTC supports a date alarm that allows for scheduling a wake up event up to 30 days in advance.

3.2.3.9General Purpose I/O (GPIO)

Various general-purpose inputs and outputs are provided for custom system design. The number of inputs and outputs varies depending on the ICH5-R configuration. All unused GPI pins are either pulled high or low, so that they are at a predefined level and do not cause undue side effects.

3.2.3.10Enhanced Power Management

The ICH5-R’s power management functions include enhanced clock control, local and global monitoring support for 14 individual devices, and various low-power (suspend) states, such as Suspend-to-DRAM and Suspend-to-Disk. A hardware-based thermal management circuit permits software-independent entrance to low-power states. The ICH5-R contains full support for the Advanced Configuration and Power Interface (ACPI) Specification, Revision 2.0b.

3.2.3.11System Management Bus (SMBus 2.0)

The ICH5-R contains an SMBus host interface that allows the processor to communicate with SMBus slaves. This interface is compatible with most I2C devices. Special I2C commands are implemented. The ICH5-R’s SMBus host controller provides a mechanism for the processor to initiate communications with SMBus peripherals (slaves).

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