Intel SE7520JR2 manual 149, Error Reporting and Handling

Intel® Server Board SE7520JR2			Table of Contents
5.3.17.2		User Model	134
5.3.17.3		Request/Response Protocol	134
5.3.17.4 Host to mBMC Communication Interface			134
5.3.17.5		LAN Interface	135
5.3.18	Event Filtering and Alerting		136
5.3.18.1 Platform Event Filtering (PEF)			136
5.3.18.2		Alert over LAN	137
5.3.19	mBMC Sensor Support		137
5.3.20	IMM BMC Sensor Support		142
5.4	Wired For Management (WFM)		148
5.5	Vital Product Data (VPD)		148
5.6	System Management BIOS (SMBIOS)		148
6. Error Reporting and Handling			149
6.1	Fault Resilient Booting (FRB)		149
6.1.1	FRB1 – BSP Self-Test Failures		149
6.1.2	FRB2 – BSP POST Failures		149
6.1.3	FRB3 – BSP Reset Failures		150
6.1.4	AP Failures		151
6.1.5	Treatment of Failed Processors		151
6.1.6	Memory Error Handling in RAS Mode		152
6.1.7	Memory Error Handling in non-RAS Mode		153
6.1.8	DIMM Enabling		154
6.1.9	Single-bit ECC Error Throttling Prevention		154
6.2	Error Logging		155
6.2.1.1		PCI Bus Error	155
6.2.1.2		Processor Bus Error	155
6.2.1.3		Memory Bus Error	156
6.2.1.4		System Limit Error	156
6.2.1.5		Processor Failure	156
6.2.1.6		Boot Event	156
6.3	Error Messages and Error Codes		156
6.3.1	POST Error Messages		156
6.3.2	POST Error Codes		162
6.3.3	BIOS Generated POST Error Beep Codes		165
6.3.4	Boot Block Error Beep Codes		166
6.3.5	BMC Generated Beep Codes (Professional/Advanced only)		166
6.4	Checkpoints		167
6.4.1	System ROM BIOS POST Task Test Point (Port 80h Code)		167
Revision 1.0		C78844-002	ix