Intel® Server Board SE7520JR2

Functional Architecture

the primary and mirror DIMMs, thereby distributing the thermal image of the workload across all populated DIMM slots, and reducing the chances of thermal-based memory traffic throttling.

In the “Mirrored” operating state, the occurrence of correctable and uncorrectable ECC errors are tracked and logged normally by the MCH, and escalated to system interrupt events as specified by the configuration register settings associated with errors on the memory subsystem. Counters implementing the “leaky bucket” function just described for on-line DIMM sparing track the aggregate count of single-bit and multiple-bit errors on a per DIMM basis.

3.3.6.7Logging Memory RAS Information to the SEL

In systems configured with either a Professional or Advanced IMM, the system BIOS is responsible for sending the current memory RAS configuration to the Sahalee BMC in accordance with Sahalee BMC spec.

Note: The operation of the memory RASUM features described is supported regardless of the platform management model used. However, with no Intel® Management Module installed, the system has limited memory monitoring and logging capabilities. It is possible for a RASUM feature to be initiated without notification that the action has occurred when using standard onboard platform instrumentation.

BIOS will send the initial memory RAS state during POST memory configuration using the SMS commands. BIOS will update the memory RAS state when memory errors occur that affect the RAS state using the SMM commands.

3.4I/O Sub-System

The I/O sub-system is made up of several components:

•The MCH provides the PCI-Express interface to the full-height riser slot

•The PXH provides the PCI-X interfaces for the two riser slots, the on-board SCSI controller and on-board Ethernet controllers

•The ICH5-R provides the interface for the onboard video controller, super IO chip, and management sub-system.

This section describes the function of each I/O interface and how they operate on the Server Board SE7520JR2.

3.4.1PCI Subsystem

The primary I/O interface for the Server Board SE7520JR2 is PCI, with four independent PCI bus segments.

•A PCI 33MHz/32-bit bus segment (P32-A) is controlled through the ICH5-R.

•Two PCI-X 100MHz/64-bit bus segments (P64-A and P64-B) are controlled through PXH PCI bridge.

•One dual x4 PCI-Express (P64-Express) bus segment is controlled from the MCH.

The table below lists the characteristics of the four PCI bus segments.

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