Status Questionable Registers
Bit Configuration of Questionable Registers
Bit Position | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
Condition | NU | UNR | RI | NU | NU | NU | NU | OT | NU | NU | OC | OV |
Bit Weight |
| 1024 | 512 | 256 | 128 | 64 | 32 | 16 | 8 | 4 | 2 | 1 |
NU = (Not used); OC = Overcurrent protection circuit has tripped.
OT = Overtemperature status condition exists; OV = Overvoltage protection circuit has tripped. RI = Remote inhibit is active; UNR = Power supply output is unregulated.
Note: See "Chapter 4 - Status Reporting" for more explanation of these registers.
STAT:QUES?
This query returns the value of the Questionable Event register. The Event register is a
Query Syntax | STATus:QUEStionable[:EVENt]? | |
Parameters | (None) |
|
Returned Parameters | <NR1> | (Register Value) |
Examples | STAT:QUES? | STATUS:QUESTIONABLE:EVENT? |
Related Commands | *CLS STAT:QUES:ENAB STAT:QUES:NTR | |
| STAT:QUES:PTR |
STAT:QUES:COND?
This query returns the value of the Questionable Condition register. That is a
Query Syntax | STATus:QUEStionable:CONDition? |
Parameters | (None) |
Examples | STAT:QUES:COND? STATUS:QUESTIONABLE:CONDITION? |
Returned Parameters | <NR1> (Register value) |
Related Commands | (None) |
STAT:QUES:ENAB
This command and its query set and read the value of the Questionable Enable register. This register is a mask for enabling specific bits from the Questionable Event register to set the questionable summary bit (QUES) of the Status Byte register. This bit (bit 3) is the logical OR of all the Questionable Event register bits that are enabled by the Questionable Status Enable register.
Command Syntax | STATus:QUEStionable:ENABle <NRf> |
Parameters | 0 to 32727 |
Suffix | (None) |
Default Value | 0 |
Examples | STAT:QUES:ENAB 20 STAT:QUES:ENAB 16 |
Query Syntax | STATus:QUEStionable:ENABle? |
Returned Parameters | <NR1> (Register value) |
Related Commands | STAT:QUES? |
Language Dictionary 43