AD9843A
DC RESTORE |
|
|
|
|
|
CDS GAIN |
|
|
|
|
|
REGISTER |
|
| INTERNAL |
|
|
|
|
|
|
| |
6 |
|
| VREF |
|
|
2dB TO 36dB |
| 2V FULL SCALE |
| ||
0.1 F CCDIN |
|
| 10 |
| |
CDS | VGA |
|
| DOUT | |
| ADC |
| |||
|
|
|
|
| |
INPUT OFFSET |
|
|
|
|
|
CLAMP |
|
|
|
| CLPOB |
|
| OPTICAL BLACK |
| ||
|
| CLAMP |
|
| |
| 10 | DAC |
|
| |
|
|
|
| ||
CLPDM |
|
| DIGITAL | 0 TO 64 LSB |
|
|
|
|
| ||
| VGA GAIN |
| FILTERING |
| |
|
|
|
| ||
|
|
|
|
| |
| REGISTER |
|
| 8 |
|
|
|
|
|
| |
|
|
|
| CLAMP LEVEL |
|
|
|
|
| REGISTER |
|
Figure 11.
CIRCUIT DESCRIPTION AND OPERATION
The AD9843A signal processing chain is shown in Figure 11. Each processing step is essential in achieving a
DC Restore
To reduce the large dc offset of the CCD output signal, a
Correlated Double Sampler
Table VII. Example CDS Gain Settings
| Recommended |
|
Max Input Signal | Gain Range | Register Code Range |
|
|
|
250 mV | 8 to 10 dB | 21 to 31 |
500 mV | 6 to 8 dB | 10 to 21 |
800 mV | 4 to 6 dB | 63 to 10 |
1 V | 2 to 4 dB | 53 to 63 |
1.25 V | 0 to 2 dB | 42 to 53 |
1.5 V | 32 to 42 | |
|
|
|
The CDS circuit samples each CCD pixel twice to extract the video information and reject
The CDS stage has a default gain of 4 dB, but uses a unique architecture that allows the CDS gain to be varied. Using the CDS Gain Register, the
| 10 |
|
|
|
|
|
|
|
|
| 8 |
|
|
|
|
|
|
|
|
– dB | 6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
CDS GAIN | 4 |
|
|
|
|
|
|
|
|
2 |
|
|
|
|
|
|
|
| |
|
|
|
|
|
|
|
|
| |
| 0 |
|
|
|
|
|
|
|
|
| 40 | 48 | 56 | 0 | 8 | 16 | 24 | 31 | |
| 32 | ||||||||
| (100000) |
|
|
|
|
|
|
| (011111) |
CDS GAIN REGISTER CODE
Figure 12. CDS Gain Curve
Input Clamp
A CDS gain of 4 dB provides some
A
Horizontal timing is shown in Figure 6. It is recommended that the CLPDM pulse be used during valid CCD dark pixels. CLPDM may be used during the optical black pixels, either
REV. 0 |