AD9843A
DEFINITIONS OF SPECIFICATIONS
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to
PEAK NONLINEARITY
Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9843A from a true straight line. The point used as “zero scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a Level 1, 1/2 LSB beyond the last code transition. The devia- tion is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC
TOTAL OUTPUT NOISE
chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB
=(ADC Full Scale/2N codes) when N is the bit resolution of the ADC. For the AD9843A, 1 LSB is 2 mV.
POWER SUPPLY REJECTION (PSR)
The PSR is measured with a step change applied to the supply pins. This represents a very
INTERNAL DELAY FOR SHP/SHD
The internal delay (also called aperture delay) is the time delay that occurs from when a sampling edge is applied to the AD9843A until the actual sample of the input signal is held. Both SHP and SHD sample the input signal during the transition from low to high, so the internal delay is measured from each clock’s rising edge to the instant the actual internal sample is taken.
The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB, and represents the rms noise level of the total signal
EQUIVALENT INPUT CIRCUITS
DVDD
330
DVSS
ACVDD
ACVSSACVSS
Figure 1. Digital
DVDDDRVDD
DATA
Figure 3. CCDIN (Pin 30)
DVDD | DVDD |
DATA IN
THREE- | DOUT | |
STATE | ||
|
DATA OUT
330
RNW
DVSS | DVSS | DVSS |
Figure 4. SDATA (Pin 47)
DVSSDRVSS
Figure 2. Data Outputs
REV. 0 |
