Analog Devices AD9843A manual Ccd-Mode And Aux-Mode Timing, CCD-Mode Timing, AUX-Mode Timing

AD9843A

CCD-MODE AND AUX-MODE TIMING

CCD

SIGNAL

tID

N N+1 N+2 N+9 N+10

tID

SHP

tS1
	tS2

SHD

tINH

DATACLK

tCP

tOD

OUTPUT	N–10
DATA

tH

N–9 N–8 N–1 N

NOTES:

1.RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.

2.CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.

Figure 5. CCD-Mode Timing

EFFECTIVE PIXELS OPTICAL BLACK PIXELS

CCD

SIGNAL

CLPOB

CLPDM

PBLK
OUTPUT	EFFECTIVE PIXEL DATA	OB PIXEL DATA
DATA

HORIZONTAL
BLANKING	DUMMY PIXELS	EFFECTIVE PIXELS

DUMMY BLACK EFFECTIVE DATA

NOTES:

1.CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB.

2.PBLK SIGNAL IS OPTIONAL.

3.DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.

Figure 6. Typical CCD-Mode Line Clamp Timing

N

VIDEO

SIGNAL

DATACLK

tOD

OUTPUT	N–10
DATA

	N+1		N+9
		N+8
tID		N+2
	tCP
	tH
N–9	N–8	N–1	N

Figure 7. AUX-Mode Timing

REV. 0 –9–