Analog Devices AD9883A manual Override Bit Function, Hspol

AD9883A

047–3 Clock Phase Adjust

A 5-bit value that adjusts the sampling phase in 32 steps across one pixel time. Each step represents an 11.25° shift in sampling phase.

The power-up default value is 16.

CLAMP TIMING

057–0 Clamp Placement

An 8-bit register that sets the position of the internally generated clamp.

When Clamp Function (Register 0Fh, Bit 7) = 0, a clamp signal is generated internally, at a position established by the clamp placement and for a duration set by the clamp duration. Clamping is started (Clamp Placement) pixel periods after the trailing edge of Hsync. The clamp place- ment may be programmed to any value between 1 and 255. Values of 0, 1, 2, 4, 8, 16, 32, 64, and 128 are not supported.

The clamp should be placed during a time that the input signal presents a stable black-level reference, usually the back porch period between Hsync and the image.

When Clamp Function = 1, this register is ignored.

067–0 Clamp Duration

An 8-bit register that sets the duration of the internally generated clamp.

For the best results, the clamp duration should be set to include the majority of the black reference signal time that follows the Hsync signal trailing edge. Insufficient clamp- ing time can produce brightness changes at the top of the screen, and a slow recovery from large changes in the Average Picture Level (APL), or brightness.

When Clamp Function = 1, this register is ignored.

Hsync PULSEWIDTH

077–0 Hsync Output Pulsewidth

An 8-bit register that sets the duration of the Hsync output pulse.

The leading edge of the Hsync output is triggered by the internally generated, phase-adjusted PLL feedback clock. The AD9883A then counts a number of pixel clocks equal to the value in this register. This triggers the trailing edge of the Hsync output, which is also phase adjusted.

INPUT GAIN

087–0 Red Channel Gain Adjust

An 8-bit word that sets the gain of the RED channel. The AD9883A can accommodate input signals with a full scale range of between 0.5 V and 1.5 V p-p. Setting REDGAIN to 255 corresponds to an input range of

1.0V. A REDGAIN of 0 establishes an input range of

0.5V. Note that INCREASING REDGAIN results in the picture having LESS CONTRAST (the input signal uses fewer of the available converter codes). See Figure 2.

097–0 Green Channel Gain Adjust

An 8-bit word that sets the gain of the GREEN channel. See REDGAIN (08).

0A 7–0 Blue Channel Gain Adjust

An 8-bit word that sets the gain of the BLUE channel. See REDGAIN (08).

INPUT OFFSET

0B 7–1 Red Channel Offset Adjust

A 7-bit offset binary word that sets the dc offset of the RED channel. One LSB of offset adjustment equals approximately one LSB change in the ADC offset. Therefore, the absolute magnitude of the offset adjustment scales as the gain of the channel is changed. A nominal setting of 63 results in the channel nominally clamping the back porch (during the clamping interval) to Code 00. An offset setting of 127 results in the channel clamping to Code 64 of the ADC. An offset setting of 0 clamps to Code –63 (off the bottom of the range). Increasing the value of Red Offset decreases the brightness of the channel.

0C 7–1 Green Channel Offset Adjust

A 7-bit offset binary word that sets the dc offset of the GREEN channel. See REDOFST (0B).

0D 7–1 Blue Channel Offset Adjust

A 7-bit offset binary word that sets the dc offset of the GREEN channel. See REDOFST (0B).

MODE CONTROL 1

0E 7 Hsync Input Polarity Override

This register is used to override the internal circuitry that determines the polarity of the Hsync signal going into the PLL.

Table IX. Hsync Input Polarity Override Settings

Override Bit	Function
0	Hsync Polarity Determined by Chip
1	Hsync Polarity Determined by User

The default for Hsync polarity override is 0 (polarity determined by chip).

0E 6 HSPOL Hsync Input Polarity

A bit that must be set to indicate the polarity of the Hsync signal that is applied to the PLL Hsync input.

Table X. Hsync Input Polarity Settings

HSPOL	Function
0	Active LOW
1	Active HIGH

Active LOW means the leading edge of the Hsync pulse is negative going. All timing is based on the leading edge of Hsync, which is the falling edge. The rising edge has no effect.

Active high is inverted from the traditional Hsync, with

apositive-going pulse. This means that timing will be based on the leading edge of Hsync, which is now the rising edge.

The device will operate if this bit is set incorrectly, but the internally generated clamp position, as established by Clamp Placement (Register 05h), will not be placed as expected, which may generate clamping errors.

The power-up default value is HSPOL = 1.

–16– REV. 0