AD9883A
Data is read from the control registers of the AD9883A in a similar manner. Reading requires two data transfer operations:
The base address must be written with the R/W bit of the slave address byte LOW to set up a sequential read operation.
Reading (the R/W bit of the slave address byte high) begins at the previously established base address. The address of the read register autoincrements after each byte is transferred.
To terminate a read/write sequence to the AD9883A, a stop signal must be sent. A stop signal comprises a
A repeated start signal occurs when the master device driving the serial interface generates a start signal without first generat- ing a stop signal to terminate the current communication. This is used to change the mode of communication (read, write) between the slave and master without releasing the serial inter- face lines.
Serial Interface Read/Write Examples
Write to one control register
➥Start Signal
➥Slave Address Byte (R/W Bit = LOW)
➥Base Address Byte
➥Data Byte to Base Address
➥Stop Signal
Write to four consecutive control registers
➥Start Signal
➥Slave Address Byte (R/W Bit = LOW)
➥Base Address Byte
➥Data Byte to Base Address
➥Data Byte to (Base Address + 1)
➥Data Byte to (Base Address + 2)
➥Data Byte to (Base Address + 3)
➥Stop Signal
Read from one control register
➥Start Signal
➥Slave Address Byte (R/W Bit = LOW)
➥Base Address Byte
➥Start Signal
➥Slave Address byte (R/W bit = HIGH)
➥Data Byte from Base Address
➥Stop Signal
Read from four consecutive control registers
➥Start Signal
➥Slave Address Byte (R/W Bit = LOW)
➥Base Address Byte
➥Start Signal
➥Slave Address Byte (R/W Bit = HIGH)
➥Data Byte from Base Address
➥Data Byte from (Base Address + 1)
➥Data Byte from (Base Address + 2)
➥Data Byte from (Base Address + 3)
➥Stop Signal
SDA | BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ACK |
SCL
Figure 11. Serial Interface—Typical Byte Transfer
| SYNC STRIPPER | ACTIVITY |
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| DETECT |
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| SYNC SEPARATOR | |||
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| NEGATIVE PEAK | COMP |
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| INTEGRATOR |
| CLAMP | SYNC |
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| VSYNC | ||
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SOG |
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| 1/S |
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| MUX 1 |
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HSYNC IN |
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| SOG OUT |
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| PLL |
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| ACTIVITY |
| POLARITY |
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| DETECT |
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| DETECT |
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| HSYNC |
| HSYNC OUT |
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| CLOCK | HSYNC OUT | |
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| MUX 2 |
| PIXEL CLOCK | |
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| GENERATOR | ||
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| COAST |
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COAST |
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| MUX 3 | POLARITY |
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| DETECT |
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| AD9883A |
VSYNC IN |
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| VSYNC OUT |
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ACTIVITY | POLARITY | MUX 4 |
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DETECT | DETECT |
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Figure 12. Sync Processing Block Diagram
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